- 26 3月, 2014 1 次提交
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由 Linus Walleij 提交于
This converts the Nomadik pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 25 3月, 2014 2 次提交
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由 Linus Walleij 提交于
The old platform data struct is just a leftover from the times when the driver was not probed exclusively from the device tree. Factor this into the general state container and simplify the probe path. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
The "secondary irq" in the nomadik pin control driver is actually not secondary (as in: can occur any time alongside the ordinary irq), it is a latent IRQ. It is an IRQ that has occurred when the system was in sleep state and has been cached in a special register flagged from the low power management unit (PRCM). Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 18 3月, 2014 2 次提交
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由 Linus Walleij 提交于
This switches the COH901 GPIO driver over to using the .request_resources() and .release_resources() callbacks from the irqchip vtable and separate the calls from the .enable() and .disable() callbacks as the latter cannot really say no to a request, whereas the resource callbacks can. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
This switches all GPIO and pin control drivers with irqchips that were using .startup() and .shutdown() callbacks to lock GPIO lines for IRQ usage over to using the .request_resources() and .release_resources() callbacks just introduced into the irqchip vtable. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 05 3月, 2014 6 次提交
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由 Barry Song 提交于
commit 655dada6 causes kernel panic, this patch fixes it. [ 1.197816] [ffffffee] *pgd=0d7fd821, *pte=00000000, *ppte=00000000 [ 1.204070] Internal error: Oops: 17 [#1] PREEMPT SMP ARM [ 1.209447] Modules linked in: [ 1.212490] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.14.0-rc1 #3 [ 1.218737] task: cd03c000 ti: cd040000 task.ti: cd040000 [ 1.224127] PC is at gpiod_lock_as_irq+0xc/0x64 [ 1.228634] LR is at sirfsoc_gpio_irq_startup+0x18/0x44 [ 1.233842] pc : [<c01d3990>] lr : [<c01d1c38>] psr: a0000193 [ 1.233842] sp : cd041d30 ip : 00000000 fp : 00000000 [ 1.245296] r10: 00000000 r9 : cd023db4 r8 : 60000113 [ 1.250505] r7 : 0000003e r6 : cd023dd4 r5 : c06bfa54 r4 : cd023d80 [ 1.257014] r3 : 00000020 r2 : 00000000 r1 : ffffffea r0 : ffffffea [ 1.263526] Flags: NzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel [ 1.270903] Control: 10c53c7d Table: 00004059 DAC: 00000015 [ 1.276631] Process swapper/0 (pid: 1, stack limit = 0xcd040240) [ 1.282620] Stack: (0xcd041d30 to 0xcd042000) [ 1.286963] 1d20: cd023d80 c01d1c38 c01d1c20 cd023d80 [ 1.295124] 1d40: 00000001 c0068438 cd023d80 ccb6d880 cd023dd4 c0067044 0000718e c006719c [ 1.286963] 1d20: cd023d80 c01d1c38 c01d1c20 cd023d80 [ 1.295124] 1d40: 00000001 c0068438 cd023d80 ccb6d880 cd023dd4 c0067044 0000718e c006719c [ 1.295124] 1d40: 00000001 c0068438 cd023d80 ccb6d880 cd023dd4 c0067044 0000718e c006719c [ 1.303283] 1d60: 00000800 00000083 ccb6d880 cd023d80 c02b41d8 00000083 0000003e ccb7c410 [ 1.311442] 1d80: 00000000 c00671dc 00000083 0000003e c02b41d8 cd3dd5c0 0000003e ccb7c634 [ 1.319601] 1da0: cd040030 c00672a8 cd3dd5c0 ccb7c410 ccb6d340 ccb7c410 ccb6d340 cd3dd400 [ 1.327760] 1dc0: cd3dd410 c02b4434 ccb7c410 c01265a8 00000001 cd3dd410 c0687108 00000000 [ 1.335919] 1de0: c0687108 00000000 00000000 c0240170 c0240158 cd3dd410 c06c30d0 c023e8bc [ 1.344079] 1e00: c023e9d4 00000000 cd3dd410 c023e9d4 c0682150 c023cf88 cd003e98 cd2d50c4 [ 1.352238] 1e20: cd3dd410 cd3dd444 c06822f0 c023e768 cd3dd418 cd3dd410 c06822f0 c023de14 [ 1.360397] 1e40: cd3dd418 00000000 cd3dd410 c023c398 cd041e78 cd041ea8 cd3dd400 cd3dd410 [ 1.368556] 1e60: 00000083 00000000 cd3dd400 cd3dd410 00000083 000000c8 c04e00c8 c023fee8 [ 1.376715] 1e80: 00000000 cd041ea8 cd3dd400 00000001 00000083 c024048c c0435ef8 c0434dec [ 1.384874] 1ea0: c068da58 c04c6d04 c0682150 c0435ef8 ffffffff 00000000 00000000 c068da58 [ 1.393033] 1ec0: 00000020 00000000 00000000 00000000 c05dabb8 00000007 c068d640 c068d640 [ 1.401193] 1ee0: c04c247c c04c249c 00000000 c00088e8 cd004c00 c043bbb8 cd029180 c03812a0 [ 1.409352] 1f00: 00000000 00000000 60000113 c0673728 60000113 c0673728 00000000 00000000 [ 1.417511] 1f20: cd7fce01 c0390a54 00000065 c003a81c c049e8bc 00000007 cd7fce0e 00000007 [ 1.425670] 1f40: 00000000 c05dabb8 00000007 c068d640 c068d640 c04c050c c04e00c8 00000065 [ 1.433829] 1f60: c04e00c0 c04c0c54 00000007 00000007 c04c050c c037d8fc cd03c000 c004322c [ 1.441988] 1f80: c0662b40 0000d640 c03737c0 00000000 00000000 00000000 00000000 00000000 [ 1.450147] 1fa0: 00000000 c03737cc 00000000 c000e478 00000000 00000000 00000000 00000000 [ 1.458307] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 1.466467] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 0002d481 05014092 [ 1.474640] [<c01d3990>] (gpiod_lock_as_irq) from [<c01d1c38>] (sirfsoc_gpio_irq_startup+0x18/0x44) [ 1.483661] [<c01d1c38>] (sirfsoc_gpio_irq_startup) from [<c0068438>] (irq_startup+0x34/0x6c) [ 1.492163] [<c0068438>] (irq_startup) from [<c0067044>] (__setup_irq+0x450/0x4b8) [ 1.499714] [<c0067044>] (__setup_irq) from [<c00671dc>] (request_threaded_irq+0xa8/0x128) [ 1.507960] [<c00671dc>] (request_threaded_irq) from [<c00672a8>] (request_any_context_irq+0x4c/0x7c) [ 1.517164] [<c00672a8>] (request_any_context_irq) from [<c02b4434>] (gpio_extcon_probe+0x144/0x1d4) [ 1.526279] [<c02b4434>] (gpio_extcon_probe) from [<c0240170>] (platform_drv_probe+0x18/0x48) [ 1.534783] [<c0240170>] (platform_drv_probe) from [<c023e8bc>] (driver_probe_device+0x120/0x238) [ 1.543641] [<c023e8bc>] (driver_probe_device) from [<c023cf88>] (bus_for_each_drv+0x58/0x8c) [ 1.552143] [<c023cf88>] (bus_for_each_drv) from [<c023e768>] (device_attach+0x74/0x88) [ 1.560126] [<c023e768>] (device_attach) from [<c023de14>] (bus_probe_device+0x84/0xa8) [ 1.568113] [<c023de14>] (bus_probe_device) from [<c023c398>] (device_add+0x440/0x520) [ 1.576012] [<c023c398>] (device_add) from [<c023fee8>] (platform_device_add+0xb4/0x214) [ 1.584084] [<c023fee8>] (platform_device_add) from [<c024048c>] (platform_device_register_full+0xb8/0xdc) [ 1.593719] [<c024048c>] (platform_device_register_full) from [<c04c6d04>] (sirfsoc_init_late+0xec/0xf4) [ 1.603185] [<c04c6d04>] (sirfsoc_init_late) from [<c04c249c>] (init_machine_late+0x20/0x28) [ 1.611603] [<c04c249c>] (init_machine_late) from [<c00088e8>] (do_one_initcall+0xf8/0x144) [ 1.619934] [<c00088e8>] (do_one_initcall) from [<c04c0c54>] (kernel_init_freeable+0x13c/0x1dc) [ 1.628620] [<c04c0c54>] (kernel_init_freeable) from [<c03737cc>] (kernel_init+0xc/0x118) Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Magnus Damm 提交于
Fix the SD1_CLK handling for r8a7791. Without this patch it is impossible to request all pins needed for SDHI1 on the Koelsch board. Signed-off-by: NMagnus Damm <damm@opensource.se> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Josh Cartwright 提交于
Modular builds of pinctrl-msm break due to handle_bad_irq being unexported for module use. For now, make PINCTRL_MSM 'bool'. Signed-off-by: NJosh Cartwright <joshc@codeaurora.org> Reviewed-by: NBjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Hans de Goede 提交于
This fixing setting the interrupt type for eints >= 8. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Hans de Goede 提交于
Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Chen-Yu Tsai 提交于
On tha Allwinner A20 SoC, the external interrupts on the pin controller device are connected to the GIC. Without chained_irq_{enter, exit}, external GPIO interrupts, such as used by mmc core card detect, cause the system to hang. This issue was first encountered during my attempt to get out-of-band interrupts for WiFi on the Cubietruck working. With David's new series of sunci-mci using mmc slot-gpio for (GPIO interrupt based) card detection, removing the SD card also causes my Cubietruck to hang. This problem should extend to all Allwinner A20 based boards. With this fix, the system no longer hangs when I remove or insert the SD card. /proc/interrupts show that the interrupt has correctly fired. However the system still does not detect card removal/insertion. I believe this is another unrelated issue. Cc: stable@vger.kernel.org Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 25 2月, 2014 1 次提交
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由 Christian Daudt 提交于
Bring the driver in line with the bcm-based dt name for pinctrl. This is being done to keep consistency with other Broadcom mobile SoC drivers. Signed-off-by: NChristian Daudt <bcm@fixthebug.org> Reviewed-by: NMatt Porter <mporter@linaro.org>
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- 06 2月, 2014 2 次提交
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由 Laxman Dewangan 提交于
When memory allocation failed, drive should return error as ENOMEM. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Florian Vaussard 提交于
Commit c420619d "pinctrl: pinconf: remove checks on ops->pin_config_get" removed the check on (ops != NULL) when performing pinconf_pins_show() or pinconf_groups_show(). As these entries are always enabled, even if pinconf is not supported, reading will result in an oops due to NULL ops. Instead of checking for ops, remove the corresponding debugfs entries if pinconf and/or pinmux are not implemented. Tested on OMAP3 (pinctrl-single). Cc: stable@vger.kernel.org Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 05 2月, 2014 1 次提交
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由 Stanislaw Gruszka 提交于
We have few fedora bug reports about list corruption on pinctrl, for example: https://bugzilla.redhat.com/show_bug.cgi?id=1051918 Most likely corruption happen due lack of protection of pinctrl_list when adding new nodes to it. Patch corrects that. Fixes: 42fed7ba ("pinctrl: move subsystem mutex to pinctrl_dev struct") Cc: stable@vger.kernel.org Signed-off-by: NStanislaw Gruszka <sgruszka@redhat.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 03 2月, 2014 5 次提交
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由 Qipan Li 提交于
according to datasheet and ac97_muxmask assignment, ac97_pins should be corrected. Signed-off-by: NQipan Li <Qipan.Li@csr.com> Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Chris Ruehl 提交于
The offset for the 2bit register calculate wrong, this patch fixes the problem. The debugfs printout for oconf, iconfa, iconfb now shows the real values. Cc: stable@vger.kernel.org Signed-off-by: NChris Ruehl <chris.ruehl@gtsys.com.hk> Reviewed-by: NMarkus Pargmann <mpa@pengutronix.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tony Prisk 提交于
Due to an assumption in the VT8500 pinctrl driver, the value passed from devicetree for 'wm,pull' was not explicitly translated before being passed to pinconf. Since v3.10, changes to 'enum pin_config_param', PIN_CONFIG_BIAS_PULL_(UP/DOWN) no longer map 1-to-1 with the expected values in devicetree. This patch adds a small translation between the devicetree values (0..2) and the enum pin_config_param equivalent values. Cc: <stable@vger.kernel.org> # v3.10+ Signed-off-by: NTony Prisk <linux@prisktech.co.nz> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Chris Ruehl 提交于
The offset to ICONFB was incorrect, this patch set the correct value 0x14. dev_dbg in function imx1_write_2bit print the wrong address and had been moved after address calculation. Cc: stable@vger.kernel.org Signed-off-by: NChris Ruehl <chris.ruehl@gtsys.com.hk> Reviewed-by: NMarkus Pargmann <mpa@pengutronix.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Nicolas Ferre 提交于
When setting the gpio irq type, use the __irq_set_handler_locked() variant instead of the irq_set_handler() to prevent false spinlock recursion warning. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Cc: stable <stable@vger.kernel.org> # v3.12 Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 21 1月, 2014 2 次提交
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由 Linus Walleij 提交于
This deletes the special AB8500 GPIO platform data passing header and merges the few remaining contents down into the abx500 pinctrl driver which handles the abx500 GPIO device. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Linus Walleij 提交于
All instances of this device are now coming from device tree- enabled platforms probing without using platform data. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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- 20 1月, 2014 1 次提交
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由 Chen-Yu Tsai 提交于
Some GPIO users, such as fixed-regulator, request GPIO output with initial value of 1. This was ignored by sunxi driver. Cc: stable@vger.kernel.org Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 18 1月, 2014 1 次提交
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由 Rafael J. Wysocki 提交于
This reverts commit f6308b36 (ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs), because it causes the Alan Cox' ASUS T100TA to "crash and burn" during boot if the Baytrail pinctrl driver is compiled in. Fixes: f6308b36 (ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs) Reported-by: NOne Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk> Requested-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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- 17 1月, 2014 1 次提交
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由 Linus Walleij 提交于
As this driver is using pinconf_generic_dt_node_to_map_pin() it needs to depend on OF so as not to cause build problems on archs that do not support OF. Cc: Sherman Yin <syin@broadcom.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 16 1月, 2014 1 次提交
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由 Sherman Yin 提交于
Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. v4: - PINCTRL selected in Kconfig, PINCTRL_CAPRI selected in bcm_defconfig - make use of regmap - change CAPRI_PIN_UPDATE from macro to inline function. - Handle pull-up strength arg in Ohm instead of enum v3: Re-work driver to be based on generic pin config. Moved config selection from Kconfig to bcm_defconfig. v2: Use hyphens instead of underscore in DT property names. Signed-off-by: NSherman Yin <syin@broadcom.com> Reviewed-by: NChristian Daudt <bcm@fixthebug.org> Reviewed-by: NMatt Porter <matt.porter@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 15 1月, 2014 6 次提交
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由 Srinivas Kandagatla 提交于
Probe function had commas instead of semi-colons on some of the lines. This patch just fixes those lines. No functional chagnes done in this patch. Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
This uses the new API for tagging GPIO lines as in use by IRQs. This enforces a few semantic checks on how the underlying GPIO line is used. Also assign the gpio_chip.dev pointer to be used for error messages. Cc: Barry Song <Baohua.Song@csr.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Barry Song 提交于
busses like i2c, spi and so on can parse the virq of their subnode automatically by irq_of_parse_and_map(). for example, i2c will do that in of_i2c_register_devices(). people can put hwirq number attached to a gpio controller in dts, and drivers can directly request the parsed virq. for example, for an i2c client as below, tangoc-ts@5c{ compatible = "pixcir,tangoc-ts"; interrupt-parent = <&gpio>; interrupts = <3 0>; reg = <0x5c>; }; in i2c client probe(), it will request_irq(client->irq, ...) without calling gpio_direction_input(). so here when we set irq type, we also put the pin to input direction. Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Barry Song 提交于
in sirfsoc gpio probe(), we create 5 irq_domains for 5 gpio banks. but in irq_create_of_mapping() of irqchip core level, irq_find_host() can only return the 1st irq_domain attached the pinctrl dt device node as we can see from the codes: unsigned int irq_create_of_mapping(struct device_node *controller, const u32 *intspec, unsigned int intsize) { struct irq_domain *domain; ... domain = controller ? irq_find_host(controller) : irq_default_domain; } struct irq_domain *irq_find_host(struct device_node *node) { struct irq_domain *h, *found = NULL; int rc; /* We might want to match the legacy controller last since * it might potentially be set to match all interrupts in * the absence of a device node. This isn't a problem so far * yet though... */ mutex_lock(&irq_domain_mutex); list_for_each_entry(h, &irq_domain_list, link) { if (h->ops->match) rc = h->ops->match(h, node); else rc = (h->of_node != NULL) && (h->of_node == node); if (rc) { found = h; break; } } mutex_unlock(&irq_domain_mutex); return found; } for sirfsoc, the 1st irq_domain attached to the device_node(controller) only can do linear for the 1st 32 gpios. so for devices who use gpio hwirq above 32 and put the information in dt like: tangoc-ts@5c{ compatible = "pixcir,tangoc-ts"; + interrupt-parent = <&gpio>; + interrupts = <34 0>; }; we will fail to get the virq for these devices as hwirq will be bigger than domain->revmap_data.linear.size in: unsigned int irq_linear_revmap(struct irq_domain *domain, irq_hw_number_t hwirq) { /* Check revmap bounds; complain if exceeded */ if (WARN_ON(hwirq >= domain->revmap_data.linear.size)) return 0; return domain->revmap_data.linear.revmap[hwirq]; } this patch drops redundant irq_domain and keep only one to fix the problem. Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tomi Valkeinen 提交于
commit 4e7e8017 (pinctrl: pinctrl-single: enhance to configure multiple pins of different modules) improved support for pinctrl-single,bits option, but also caused a regression in parsing badly configured mask data. If the masks in DT data are not quite right, pcs_parse_bits_in_pinctrl_entry() can end up in an infinite loop, trashing memory at the same time. Add a check to verify that each loop actually removes bits from the 'mask', so that the loop can eventually end. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tomi Valkeinen 提交于
pcs_enable() uses vals->mask instead of pcs->fmask when bits_per_mux is enabled. However, pcs_disable() always uses pcs->fmask. Fix pcs_disable() to use vals->mask with bits_per_mux. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 14 1月, 2014 1 次提交
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由 Mallikarjun Kasoju 提交于
If pins are used for function output like pwm, clk32k, power good etc then set it as output mode default. Signed-off-by: NMallikarjun Kasoju <mkasoju@nvidia.com> Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Acked-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 08 1月, 2014 6 次提交
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由 Mika Westerberg 提交于
Instead of asking each driver to register to ACPI events we can just call acpi_gpiochip_register_interrupts() for each chip that has an ACPI handle. The function checks chip->to_irq and if it is set to NULL (a GPIO driver that doesn't do interrupts) the function does nothing. We also add the a new header drivers/gpio/gpiolib.h that is used for functions internal to gpiolib and add ACPI GPIO chip registering functions to that header. Once that is done we can remove call to acpi_gpiochip_register_interrupts() from its only user, pinctrl-baytrail.c Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Acked-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Rongjun Ying 提交于
USP0 has multiple functions, and has RX and TX frame sync signals, for some scenarios like audio PCM, we don't need both of them. so here we add two possibilities for USP0 only holding one of TX and RX frame sync. Signed-off-by: NRongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: NBarry Song <Barry.Song@csr.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Bin Shi 提交于
sdmmc5 has only 3 pins CMD, CLK, DATA which are connected with CSR TriG RF multi-GNSS. The hardware connection is like: DATA -- GPS_SGN CLK -- GPS_RF_CLK CMD -- GPS_MAG here we drop redundant pins in sdmmc5 group. Signed-off-by: NBin Shi <Bin.Shi@csr.com> Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Qipan Li 提交于
commit af614b23 adds lost USP-based UART pin groups for prima2, but missed usp1_uart_nostreamctrl group for atlas6, this patch fixes it. this makes USP(Universal Serial Ports) port1 can work as uart without stream ctrl. Signed-off-by: NQipan Li <Qipan.Li@csr.com> Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Chen-Yu Tsai 提交于
This patch adds the clock output pin functions on the A20. The 2 pins can output a configurable clock to be used by external modules. This is used on the CubieTruck, to supply a 32768 Hz low power clock to the onboard Wifi+BT module. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Antonios Vamporakis 提交于
Signed-off-by: NAntonios Vamporakis <ant@area128.com> CC: John Crispin <blogic@openwrt.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 07 1月, 2014 1 次提交
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由 Valentine Barshak 提交于
This adds I2C[0-4] pinmux support to R8A7791 SoC. Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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