- 25 7月, 2011 1 次提交
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由 Benjamin Herrenschmidt 提交于
The writeback ring pointer and IH ring pointer are read using le32_to_cpu so we do not want the chip to byteswap them on big-endian. We still want to byteswap the ring itself and the IBs, so we don't touch that but we remove setting of the byteswap bits in CP_RB_RPTR_ADDR and IH_CNTL. In general, for things like that where we control all the accessors easily, we are better off doing the swap in SW rather than HW. Paradoxally, it does keep the code closer to x86 and avoid using poorly tested HW features. I also changed the use of RADEON_ to R600_ in a couple of cases to be more consistent with the surrounding code. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NMichel Dänzer <michel@daenzer.net> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 18 7月, 2011 1 次提交
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由 Alex Deucher 提交于
The 3D driver need to get the pipe to backend map to certain things. Add a query to get the info. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 07 7月, 2011 1 次提交
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由 Jerome Glisse 提交于
ib pool weren't free for various newer asic on module unload. This doesn't cause much arm but still could be candidate for stable. Signed-off-by: NJerome Glisse <jglisse@redhat.com> cc: stable@kernel.org Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 21 6月, 2011 1 次提交
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由 Alex Deucher 提交于
0xff01 is not an actual voltage value, but a flag for the driver. If the power state as that value, skip setting the voltage. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 20 6月, 2011 1 次提交
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由 Dave Airlie 提交于
Since we were calling the wptr function before checking if the IH was even enabled, or the GPU wasn't shutdown, we'd get spam in the logs when the GPU readback 0xffffffff. This reorders things so we return early in the no IH and GPU shutdown cases. Reported-and-tested-by: ManDay on #radeon Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 09 6月, 2011 1 次提交
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由 Ilija Hadzic 提交于
debug statement for GUI idle interrupt is wrong and incorrectly reports CP EOP interrupt; trivial issue, but confusing for someone trying to distinguish interrupt sources while debugging ... fixed Signed-off-by: NIlija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 02 6月, 2011 1 次提交
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由 Alex Deucher 提交于
- add gpu init support - add blit support - add ucode loader Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 20 4月, 2011 1 次提交
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由 Cédric Cano 提交于
agd5f: fix commit message. Signed-off-by: NCedric Cano <ccano@interfaceconcept.com> Reviewed-by: NMichel Dänzer <michel@daenzer.net> Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 13 4月, 2011 2 次提交
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由 Alex Deucher 提交于
This is needed for setting voltages other than vddc. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
As per Konrad's original patch, the dummy page used by the gart code and allocated in radeon_gart_init() was not freed properly in radeon_gart_fini(). At the same time r6xx and newer allocated and freed the dummy page on their own. So to do Konrad's patch one better, just remove the allocation and freeing of the dummy page in the r6xx, 7xx, evergreen, and ni code and allocate and free in the gart_init/fini() functions for all asics. Cc: Jerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Acked-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 14 3月, 2011 1 次提交
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由 Dave Airlie 提交于
So we used to use lpfn directly to restrict VRAM when we couldn't access the unmappable area, however this was removed in 93225b0d as it also restricted the gtt placements. However it was only later noticed that this broke on some hw. This removes the active_vram_size, and just explicitly sets it when it changes, TTM/drm_mm will always use the real_vram_size, and the active vram size will change the TTM size used for lpfn setting. We should re-work the fpfn/lpfn to per-placement at some point I suspect, but that is too late for this kernel. Hopefully this addresses: https://bugs.freedesktop.org/show_bug.cgi?id=35254 v2: fix reported useful VRAM size to userspace to be correct. Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 03 3月, 2011 1 次提交
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 23 2月, 2011 1 次提交
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由 Daniel Vetter 提交于
Unconditionally initialize the drm gem object - it's not worth the trouble not to for the few kernel objects. This patch only changes the place of the drm gem object, access is still done via pointers. v2: Uncoditionally align the size in radeon_bo_create. At least the r600/evergreen blit code didn't to this, angering the paranoid gem code. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 17 2月, 2011 1 次提交
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由 Paul Bolle 提交于
Signed-off-by: NPaul Bolle <pebolle@tiscali.nl> Signed-off-by: NJiri Kosina <jkosina@suse.cz>
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- 14 2月, 2011 1 次提交
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由 Cédric Cano 提交于
agd5f: minor cleanups Signed-off-by: NCédric Cano <ccano@interfaceconcept.com> Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 02 2月, 2011 1 次提交
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由 Alex Deucher 提交于
Some fixes to the thermal sensor code: - handle negative numbers - properly handle temp calculation on different asics Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 24 1月, 2011 1 次提交
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由 Alex Deucher 提交于
Don't reset if the engine isn't busy. This matches the behavior of previous asics. Reseting a non-hung block can lead to a hang. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=33272Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@gmail.com>
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- 17 1月, 2011 2 次提交
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由 Alex Deucher 提交于
Use the common one for all asics. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Switching to pcie gen2 causes problems on some boards. Add a module option to turn it on/off. There are gen2 compatability issues with some motherboards it seems. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=33027Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 07 1月, 2011 2 次提交
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由 Alex Deucher 提交于
Supported on rv6xx/r7xx/evergreen. Cards come up in gen1 mode. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 06 1月, 2011 1 次提交
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由 Tejun Heo 提交于
With cmwq, there's no reason for radeon to use a dedicated workqueue. Drop dev_priv->wq and use system_wq instead. Because radeon_driver_irq_uninstall_kms() may be called from unsleepable context, the work items can't be flushed from there. Instead, init and flush from radeon_irq_kms_init/fini(). While at it, simplify canceling/flushing of rdev->pm.dynpm_idle_work. Always initialize and sync cancel instead of being unnecessarily smart about it. Signed-off-by: NTejun Heo <tj@kernel.org> Acked-by: NAlex Deucher <alexdeucher@gmail.com> Cc: dri-devel@lists.freedesktop.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 22 12月, 2010 1 次提交
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由 Alex Deucher 提交于
We were using the lockup struct from the wrong union. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Cc: Jerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 09 12月, 2010 1 次提交
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由 Alex Deucher 提交于
It should be required for all 7xx asics, but seems to cause problems on some AGP 7xx chips. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=19002Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Reported-and-Tested-by: NDuncan <1i5t5.duncan@cox.net> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 08 12月, 2010 1 次提交
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由 Alex Deucher 提交于
Avoid overflowing a 32 bit value. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 23 11月, 2010 2 次提交
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
MC_VM_FB_LOCATION is at a different offset between r6xx and r7xx/evergreen. The location is needed for vram setup on fusion chips. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 22 11月, 2010 2 次提交
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由 Mario Kleiner 提交于
In the vblank irq handler, calls to actual vblank handling, or at least drm_handle_vblank(), need to happen before calls to radeon_crtc_handle_flip(). Reason: The high precision pageflip timestamping and some other pageflip optimizations will need the updated vblank count and timestamps for the current vblank interval. These are calculated in drm_handle_vblank(), therefore it must go first. Signed-off-by: NMario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
This adds support for dri2 pageflipping. v2: precision updates from Mario Kleiner. v3: Multihead fixes from Mario Kleiner; missing crtc offset add note about update pending bit on pre-avivo chips Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NMario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 18 11月, 2010 1 次提交
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由 Alex Deucher 提交于
We were previously dropping alignment requests on the floor when allocating buffers so we always ended up page aligned. Certain tiling modes on 6xx+ require larger alignment which wasn't happening before. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Cc: Jerome Glisse <j.glisse@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 09 11月, 2010 2 次提交
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由 Alex Deucher 提交于
Temperature is not shifted as on newer asics. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Joe Perches 提交于
Coalesce long formats. Align arguments. Add missing newlines. Signed-off-by: NJoe Perches <joe@perches.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 26 10月, 2010 1 次提交
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由 Alex Deucher 提交于
Needed for tiled surfaces. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 12 10月, 2010 2 次提交
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由 Alex Deucher 提交于
These bits are used for internal communication and should be left enabled. This may fix s/r issues on some systems. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Jerome Glisse 提交于
We should not allocate any object into unmappable vram if we have no means to access them which on all GPU means having the CP running and on newer GPU having the blit utility working. This patch limit the vram allocation to visible vram until we have acceleration up and running. Note that it's more than unlikely that we run into any issue related to that as when acceleration is not woring userspace should allocate any object in vram beside front buffer which should fit in visible vram. V2 use real_vram_size as mc_vram_size could be bigger than the actual amount of vram [airlied: fixup r700_cp_stop case] Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 06 10月, 2010 3 次提交
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由 Alex Deucher 提交于
On r6xx+ a newer fence mechanism was implemented to replace the old wait_until plus scratch regs setup. A single EOP event will flush the destination caches, write a fence value, and generate an interrupt. This is the recommended fence mechanism on r6xx+ asics. This requires my previous writeback patch. v2: fix typo that enabled event fence checking on all asics rather than just r6xx+. v3: properly enable EOP interrupts Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=29972Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
When writeback is enabled, the GPU shadows writes to certain registers into a buffer in memory. The driver can then read the values from the shadow rather than reading back from the register across the bus. Writeback can be disabled by setting the no_wb module param to 1. On r6xx/r7xx/evergreen, the following registers are shadowed: - CP scratch registers - CP read pointer - IH write pointer On r1xx-rr5xx, the following registers are shadowed: - CP scratch registers - CP read pointer v2: - Combine wb patches for r6xx-evergreen and r1xx-r5xx - Writeback is disabled on AGP boards since it tends to be unreliable on AGP using the gart. - Check radeon_wb_init return values properly. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Move common code to init function. v2: make sure the bo is pinned after init as well. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 28 9月, 2010 1 次提交
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由 Alex Deucher 提交于
radeon_gem_wait_idle_ioctl can apparently get called prior to the vram page being set up or even if accel if false, so make sure it's valid before using it. Should fix: http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=597636 https://bugs.freedesktop.org/show_bug.cgi?id=29834Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 24 9月, 2010 1 次提交
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由 Daniel J Blueman 提交于
Fix string interpreted as trigraph and typo. Signed-off-by: NDaniel J Blueman <daniel.blueman@gmail.com> Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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