1. 01 7月, 2009 1 次提交
  2. 18 6月, 2009 2 次提交
  3. 16 1月, 2009 1 次提交
  4. 21 10月, 2008 1 次提交
  5. 19 8月, 2008 1 次提交
    • L
      [IA64] pci_acpi_scan_root cleanup · 8a20fd52
      Luck, Tony 提交于
      The code walks all the acpi _CRS methods to see how many windows
      to allocate.  It then scans them all again to insert_resource()
      for each *even if the first scan found that there were none*.
      
      Move the second scan inside the "if (windows)" clause.
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      8a20fd52
  6. 21 4月, 2008 1 次提交
  7. 16 4月, 2008 1 次提交
  8. 07 3月, 2008 1 次提交
  9. 11 2月, 2008 1 次提交
  10. 26 7月, 2007 1 次提交
  11. 12 7月, 2007 1 次提交
    • A
      [IA64] prevent MCA when performing MMIO mmap to PCI config space · 012b7105
      Alex Chiang 提交于
      Example memory map (HP rx7640 with 'default' acpiconfig setting, VGA disabled):
         0x00000000 - 0x3FFFBFFF  supports only WB (cacheable) access
      
      If a user attempts to perform an MMIO mmap (using the PCIIOC_MMAP_IS_MEM ioctl)
      to PCI config space (like mmap'ing and accessing memory at 0xA0000),
      we will MCA because the kernel will attempt to use a mapping with the UC
      attribute.
      
      So check the memory attribute in kern_mmap and the EFI memmap. If WC is
      requested, and WC or UC access is supported for the region, allow it.
      Otherwise, use the same attribute the kernel uses.
      
      Updates documentation and test cases as well.
      Signed-off-by: NAlex Chiang <achiang@hp.com>
      Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      012b7105
  12. 23 5月, 2007 1 次提交
  13. 09 5月, 2007 1 次提交
  14. 31 3月, 2007 1 次提交
  15. 30 3月, 2007 1 次提交
  16. 29 3月, 2007 1 次提交
  17. 08 12月, 2006 1 次提交
  18. 07 12月, 2006 1 次提交
  19. 02 12月, 2006 2 次提交
    • J
      Altix: Add initial ACPI IO support · 8ea6091f
      John Keller 提交于
      First phase in introducing ACPI support to SN.
      In this phase, when running with an ACPI capable PROM,
      the DSDT will define the root busses and all SN nodes
      (SGIHUB, SGITIO). An ACPI bus driver will be registered
      for the node devices, with the acpi_pci_root_driver being
      used for the root busses. An ACPI vendor descriptor is
      now used to pass platform specific information for both
      nodes and busses, eliminating the need for the current
      SAL calls. Also, with ACPI support, SN fixup code is no longer
      needed to initiate the PCI bus scans, as the acpi_pci_root_driver
      does that.
      
      However, to maintain backward compatibility with non-ACPI capable
      PROMs, none of the current 'fixup' code can been deleted, though
      much restructuring has been done. For example, the bulk of the code
      in io_common.c is relocated code that is now common regardless
      of what PROM is running, while io_acpi_init.c and io_init.c contain
      routines specific to an ACPI or non ACPI capable PROM respectively.
      
      A new pci bus fixup platform vector has been created to provide
      a hook for invoking platform specific bus fixup from pcibios_fixup_bus().
      
      The size of io_space[] has been increased to support systems with
      large IO configurations.
      Signed-off-by: NJohn Keller <jpk@sgi.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      
      8ea6091f
    • M
      PCI: Use pci_generic_prep_mwi on ia64 · 3efe2d84
      Matthew Wilcox 提交于
      The pci_generic_prep_mwi() code does everything that pcibios_prep_mwi()
      does on ia64.  All we need to do is be sure that pci_cache_line_size
      is set appropriately, and we can delete pcibios_prep_mwi().
      
      Using SMP_CACHE_BYTES as the default was wrong on uniprocessor machines
      as it is only 8 bytes.  The default in the generic code of L1_CACHE_BYTES
      is at least as good.
      Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
      Acked-by: NJeff Garzik <jeff@garzik.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      3efe2d84
  20. 04 10月, 2006 1 次提交
    • E
      [PATCH] genirq: msi: simplify the msi irq limit policy · 92db6d10
      Eric W. Biederman 提交于
      Currently we attempt to predict how many irqs we will be able to allocate with
      msi using pci_vector_resources and some complicated accounting, and then we
      only allow each device as many irqs as we think are available on average.
      
      Only the s2io driver even takes advantage of this feature all other drivers
      have a fixed number of irqs they need and bail if they can't get them.
      
      pci_vector_resources is inaccurate if anyone ever frees an irq.  The whole
      implmentation is racy.  The current irq limit policy does not appear to make
      sense with current drivers.  So I have simplified things.  We can revisit this
      we we need a more sophisticated policy.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      92db6d10
  21. 27 9月, 2006 1 次提交
  22. 11 7月, 2006 1 次提交
    • L
      [PATCH] make valid_mmap_phys_addr_range() take a pfn · 06c67bef
      Lennert Buytenhek 提交于
      Newer ARMs have a 40 bit physical address space, but mapping physical
      memory above 4G needs a special page table format which we (currently?) do
      not use for userspace mappings, so what happens instead is that mapping an
      address >= 4G will happily discard the upper bits and wrap.
      
      There is a valid_mmap_phys_addr_range() arch hook where we could check for
      >= 4G addresses and deny the mapping, but this hook takes an unsigned long
      address:
      
      	static inline int valid_mmap_phys_addr_range(unsigned long addr, size_t size);
      
      And drivers/char/mem.c:mmap_mem() calls it like this:
      
      	static int mmap_mem(struct file * file, struct vm_area_struct * vma)
      	{
      		size_t size = vma->vm_end - vma->vm_start;
      
      		if (!valid_mmap_phys_addr_range(vma->vm_pgoff << PAGE_SHIFT, size))
      
      So that's not much help either.
      
      This patch makes the hook take a pfn instead of a phys address.
      Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
      Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Cc: Russell King <rmk@arm.linux.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      06c67bef
  23. 01 7月, 2006 1 次提交
  24. 28 6月, 2006 1 次提交
  25. 26 6月, 2006 1 次提交
  26. 23 6月, 2006 1 次提交
  27. 09 5月, 2006 1 次提交
    • B
      [IA64] rework memory attribute aliasing · 32e62c63
      Bjorn Helgaas 提交于
      This closes a couple holes in our attribute aliasing avoidance scheme:
      
        - The current kernel fails mmaps of some /dev/mem MMIO regions because
          they don't appear in the EFI memory map.  This keeps X from working
          on the Intel Tiger box.
      
        - The current kernel allows UC mmap of the 0-1MB region of
          /sys/.../legacy_mem even when the chipset doesn't support UC
          access.  This causes an MCA when starting X on HP rx7620 and rx8620
          boxes in the default configuration.
      
      There's more detail in the Documentation/ia64/aliasing.txt file this
      adds, but the general idea is that if a region might be covered by
      a granule-sized kernel identity mapping, any access via /dev/mem or
      mmap must use the same attribute as the identity mapping.
      
      Otherwise, we fall back to using an attribute that is supported
      according to the EFI memory map, or to using UC if the EFI memory
      map doesn't mention the region.
      Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      32e62c63
  28. 21 4月, 2006 1 次提交
    • S
      [IA64] eliminate compile time warnings · a72391e4
      Satoru Takeuchi 提交于
      This patch removes following compile time warnings:
      
      drivers/pci/pci-sysfs.c: In function `pci_read_legacy_io':
      drivers/pci/pci-sysfs.c:257: warning: implicit declaration of function `ia64_pci_legacy_read'
      drivers/pci/pci-sysfs.c: In function `pci_write_legacy_io':
      drivers/pci/pci-sysfs.c:280: warning: implicit declaration of function `ia64_pci_legacy_write'
      
      It also fixes wrong definition of ia64_pci_legacy_write (type of `bus' is not
      `pci_dev', but `pci_bus').
      Signed-Off-By: NSatoru Takeuchi <takeuchi_satoru@jp.fujitsu.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      a72391e4
  29. 28 2月, 2006 1 次提交
  30. 17 1月, 2006 1 次提交
  31. 04 1月, 2006 1 次提交
  32. 10 12月, 2005 2 次提交
    • B
      [ACPI] ACPICA 20051021 · 0897831b
      Bob Moore 提交于
      Implemented support for the EM64T and other x86_64
      processors. This essentially entails recognizing
      that these processors support non-aligned memory
      transfers. Previously, all 64-bit processors were assumed
      to lack hardware support for non-aligned transfers.
      
      Completed conversion of the Resource Manager to nearly
      full table-driven operation. Specifically, the resource
      conversion code (convert AML to internal format and the
      reverse) and the debug code to dump internal resource
      descriptors are fully table-driven, reducing code and data
      size and improving maintainability.
      
      The OSL interfaces for Acquire and Release Lock now use a
      64-bit flag word on 64-bit processors instead of a fixed
      32-bit word. (Alexey Starikovskiy)
      
      Implemented support within the resource conversion code
      for the Type-Specific byte within the various ACPI 3.0
      *WordSpace macros.
      
      Fixed some issues within the resource conversion code for
      the type-specific flags for both Memory and I/O address
      resource descriptors. For Memory, implemented support
      for the MTP and TTP flags. For I/O, split the TRS and TTP
      flags into two separate fields.
      Signed-off-by: NBob Moore <robert.moore@intel.com>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      0897831b
    • B
      [ACPI] ACPICA 20050930 · 50eca3eb
      Bob Moore 提交于
      Completed a major overhaul of the Resource Manager code -
      specifically, optimizations in the area of the AML/internal
      resource conversion code. The code has been optimized to
      simplify and eliminate duplicated code, CPU stack use has
      been decreased by optimizing function parameters and local
      variables, and naming conventions across the manager have
      been standardized for clarity and ease of maintenance (this
      includes function, parameter, variable, and struct/typedef
      names.)
      
      All Resource Manager dispatch and information tables have
      been moved to a single location for clarity and ease of
      maintenance. One new file was created, named "rsinfo.c".
      
      The ACPI return macros (return_ACPI_STATUS, etc.) have
      been modified to guarantee that the argument is
      not evaluated twice, making them less prone to macro
      side-effects. However, since there exists the possibility
      of additional stack use if a particular compiler cannot
      optimize them (such as in the debug generation case),
      the original macros are optionally available.  Note that
      some invocations of the return_VALUE macro may now cause
      size mismatch warnings; the return_UINT8 and return_UINT32
      macros are provided to eliminate these. (From Randy Dunlap)
      
      Implemented a new mechanism to enable debug tracing for
      individual control methods. A new external interface,
      acpi_debug_trace(), is provided to enable this mechanism. The
      intent is to allow the host OS to easily enable and disable
      tracing for problematic control methods. This interface
      can be easily exposed to a user or debugger interface if
      desired. See the file psxface.c for details.
      
      acpi_ut_callocate() will now return a valid pointer if a
      length of zero is specified - a length of one is used
      and a warning is issued. This matches the behavior of
      acpi_ut_allocate().
      Signed-off-by: NBob Moore <robert.moore@intel.com>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      50eca3eb
  33. 09 11月, 2005 1 次提交
    • B
      [IA64] add the MMIO regions that are translated to I/O port space to /proc/iomem · 4f41d5a4
      Bjorn Helgaas 提交于
      ia64 translates normal loads and stores to special MMIO regions into I/O port
      accesses.  Reserve these special MMIO regions in /proc/iomem.
      
      Sample /proc/iomem:
          f8100000000-f81003fffff : PCI Bus 0000:80 I/O Ports 00000000-00000fff
          f8100400000-f81007fffff : PCI Bus 0000:8e I/O Ports 00001000-00001fff
          f8100800000-f8100ffffff : PCI Bus 0000:9c I/O Ports 00002000-00003fff
          f8101000000-f81017fffff : PCI Bus 0000:aa I/O Ports 00004000-00005fff
      
      and corresponding /proc/ioports:
          00000000-00000fff : PCI Bus 0000:80
          00001000-00001fff : PCI Bus 0000:8e
          00002000-00003fff : PCI Bus 0000:9c
          00004000-00005fff : PCI Bus 0000:aa
      Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      4f41d5a4
  34. 24 9月, 2005 1 次提交
  35. 20 9月, 2005 1 次提交
  36. 08 9月, 2005 1 次提交
  37. 25 8月, 2005 1 次提交