1. 25 3月, 2017 1 次提交
  2. 15 2月, 2017 3 次提交
  3. 14 2月, 2017 1 次提交
  4. 07 2月, 2017 2 次提交
    • S
      net/mlx5: TX WQE update · 2b31f7ae
      Saeed Mahameed 提交于
      Add new TX WQE fields for Connect-X5 vlan insertion support,
      type and vlan_tci, when type = MLX5_ETH_WQE_INSERT_VLAN the
      HW will insert the vlan and prio fields (vlan_tci) to the packet.
      
      Those bits and the inline header fields are mutually exclusive, and
      valid only when:
      MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_NOT_REQUIRED
      and MLX5_CAP_ETH(mdev, wqe_vlan_insert),
      who will be set in ConnectX-5 and later HW generations.
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      Reviewed-by: NTariq Toukan <tariqt@mellanox.com>
      2b31f7ae
    • D
      net/mlx5: Configure cache line size for start and end padding · f32f5bd2
      Daniel Jurgens 提交于
      There is a hardware feature that will pad the start or end of a DMA to
      be cache line aligned to avoid RMWs on the last cache line. The default
      cache line size setting for this feature is 64B. This change configures
      the hardware to use 128B alignment on systems with 128B cache lines.
      
      In addition we lower bound MPWRQ stride by HCA cacheline in mlx5e,
      MPWRQ stride should be at least the HCA cacheline, the current default
      is 64B and in case HCA_CAP.cach_line_128byte capability is set, MPWRQ RX
      stride will automatically be aligned to 128B.
      Signed-off-by: NDaniel Jurgens <danielj@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      f32f5bd2
  5. 06 2月, 2017 1 次提交
  6. 25 1月, 2017 2 次提交
  7. 20 1月, 2017 7 次提交
  8. 10 1月, 2017 4 次提交
  9. 08 1月, 2017 2 次提交
  10. 03 1月, 2017 8 次提交
  11. 29 12月, 2016 1 次提交
  12. 14 12月, 2016 1 次提交
  13. 02 12月, 2016 1 次提交
  14. 29 11月, 2016 2 次提交
  15. 25 11月, 2016 1 次提交
  16. 19 11月, 2016 3 次提交