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  1. 27 10月, 2010 1 次提交
  3. 17 7月, 2010 1 次提交
    • B
      PCI: fall back to original BIOS BAR addresses · 58c84eda
      由 Bjorn Helgaas 提交于 
      If we fail to assign resources to a PCI BAR, this patch makes us try the
original address from BIOS rather than leaving it disabled.

Linux tries to make sure all PCI device BARs are inside the upstream
PCI host bridge or P2P bridge apertures, reassigning BARs if necessary.
Windows does similar reassignment.

Before this patch, if we could not move a BAR into an aperture, we left
the resource unassigned, i.e., at address zero.  Windows leaves such BARs
at the original BIOS addresses, and this patch makes Linux do the same.

This is a bit ugly because we disable the resource long before we try to
reassign it, so we have to keep track of the BIOS BAR address somewhere.
For lack of a better place, I put it in the struct pci_dev.

I think it would be cleaner to attempt the assignment immediately when the
claim fails, so we could easily remember the original address.  But we
currently claim motherboard resources in the middle, after attempting to
claim PCI resources and before assigning new PCI resources, and changing
that is a fairly big job.

Addresses https://bugzilla.kernel.org/show_bug.cgi?id=16263Reported-by: NAndrew <nitr0@seti.kr.ua>
Tested-by: NAndrew <nitr0@seti.kr.ua>
Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      58c84eda
  5. 12 6月, 2010 1 次提交
  7. 27 4月, 2010 1 次提交
  9. 25 3月, 2010 1 次提交
  11. 23 2月, 2010 2 次提交
  13. 11 2月, 2010 1 次提交
  15. 05 12月, 2009 1 次提交
  17. 05 11月, 2009 4 次提交
  19. 28 9月, 2009 1 次提交
  21. 11 7月, 2009 1 次提交
    • Y
      x86/pci: insert ioapic resource before assigning unassigned resources · 857fdc53
      由 Yinghai Lu 提交于 
      Stephen reported that his DL585 G2 needed noapic after 2.6.22 (?)

Dann bisected it down to:
  commit 30a18d6c
  Date:   Tue Feb 19 03:21:20 2008 -0800

      x86: multi pci root bus with different io resource range, on
      64-bit

It turns out that:
  1. that AMD-based systems have two HT chains.
  2. BIOS doesn't allocate resources for BAR 6 of devices under 8132 etc
  3. that multi-peer-root patch will try to split root resources to peer
     root resources according to PCI conf of NB
  4. PCI core assigns unassigned resources, but they overlap with BARs
     that are used by ioapic addr of io4 and 8132.

The reason: at that point ioapic address are not inserted yet.  Solution
is to insert ioapic resources into the tree a bit earlier.
Reported-by: NStephen Frost <sfrost@snowman.net>
Reported-and-Tested-by: Ndann frazier <dannf@hp.com>
Signed-off-by: NYinghai Lu <yinghai@kernel.org>
Cc: stable@kernel.org
Signed-off-by: NJesse Barnes <jbarnes@jbarnes-g45.(none)>
      857fdc53
  23. 18 6月, 2009 1 次提交
  25. 23 4月, 2009 1 次提交
  27. 04 4月, 2009 1 次提交
    • S
      x86, PAT: Remove duplicate memtype reserve in pci mmap · 5a3ae276
      由 Suresh Siddha 提交于 
      pci mmap code was doing memtype reserve for a while now. Recently we
added memtype tracking in remap_pfn_range, and pci code indirectly calls
remap_pfn_range. So, we don't need seperate tracking in pci code
anymore. Which means a patch that removes ~50 lines of code :-).

Also, recently we found out that the pci tracking is not working as we expect
it to work in some cases. Specifically, userlevel X mmap of pci, with some
recent version of X, is having a problem with vm_page_prot getting reset.
The pci tracking uses vm_page_prot to pass on the protection type from parent
to child during fork.
a) Parent does a pci mmap
b) We look at PAT and get either UC_MINUS or WC mapping for parent
c) Store that mapping type in vma vm_page_prot for future use
d) This thread does a fork
e) Fork results in mmap_ops ->open for the child process
f) We get the vm_page_prot from vma and reserve that type for the child process

But, between c) and e) above, the vma vm_page_prot is getting reset to zero.
This results in PAT reserve failing at the time of fork as in here.
http://marc.info/?l=linux-kernel&m=123858163103240&w=2

This cleanup makes the above problem go away as we do not depend on
vm_page_prot in our PAT code anymore.
Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      5a3ae276
  29. 24 3月, 2009 1 次提交
  31. 14 1月, 2009 1 次提交
  33. 08 1月, 2009 1 次提交
  35. 30 12月, 2008 1 次提交
  37. 04 9月, 2008 2 次提交
  39. 03 9月, 2008 1 次提交
    • L
      Un-break printk strings in x86 PCI probing code · 011fec74
      由 Linus Torvalds 提交于 
      Breaking lines due to some imaginary problem with a long line length is
often stupid and wrong, but never more so when it splits a string that
is printed out into multiple lines.  This really ended up making it much
harder to find where some error strings were printed out, because a
simple 'grep' didn't work.

I'm sure there is tons more of this particular idiocy hiding in other
places, but this particular case hit me once more last week. So fix it.
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      011fec74
  41. 30 8月, 2008 1 次提交
  43. 25 8月, 2008 1 次提交
    • Y
      x86: fix HPET regression in 2.6.26 versus 2.6.25, check hpet against BAR, v3 · a2bd7274
      由 Yinghai Lu 提交于 
      David Witbrodt tracked down (and bisected) a hpet bootup hang on his
system to the following problem: a BIOS bug made the hpet device
visible as a generic PCI device. If e820 reserved entries happen to
be registered first in the resource tree [which v2.6.26 started doing],
then the PCI code will reallocate that device's BAR to some other
address - breaking timer IRQs and hanging the system.

( Normally hpet devices are hidden by the BIOS from the OS's PCI
  discovery via chipset magic. Sometimes the hpet is not a PCI device
  at all. )

Solve this fundamental fragility by making non-PCI platform drivers
insert resources into the resource tree even if it overlaps the e820
reserved entry, to keep the resource manager from updating the BAR.

Also do these checks for the ioapic and mmconfig addresses, and emit
a warning if this happens.
Bisected-by: NDavid Witbrodt <dawitbro@sbcglobal.net>
Signed-off-by: NYinghai Lu <yhlu.kernel@gmail.com>
Tested-by: NDavid Witbrodt <dawitbro@sbcglobal.net>
Signed-off-by: NIngo Molnar <mingo@elte.hu>
      a2bd7274
  45. 29 7月, 2008 1 次提交
  47. 25 7月, 2008 1 次提交
  49. 13 7月, 2008 1 次提交
  51. 11 7月, 2008 1 次提交
  53. 12 6月, 2008 1 次提交
  55. 14 5月, 2008 1 次提交
  57. 01 5月, 2008 1 次提交
    • S
      x86 PAT: fix performance drop for glx, use UC minus for ioremap(),... · de33c442
      由 Suresh Siddha 提交于 
      x86 PAT: fix performance drop for glx, use UC minus for ioremap(), ioremap_nocache() and pci_mmap_page_range()

Use UC_MINUS for ioremap(), ioremap_nocache() instead of strong UC.
Once all the X drivers move to ioremap_wc(), we can go back to strong
UC semantics for ioremap() and ioremap_nocache().

To avoid attribute aliasing issues, pci_mmap_page_range() will also
use UC_MINUS for default non write-combining mapping request.

Next steps:
	a) change all the video drivers using ioremap() or ioremap_nocache()
	   and adding WC MTTR using mttr_add() to ioremap_wc()

	b) for strict usage, we can go back to strong uc semantics
	   for ioremap() and ioremap_nocache() after some grace period for
	   completing step-a.

	c) user level X server needs to use the appropriate method for setting
	   up WC mapping (like using resourceX_wc sysfs file instead of
	   adding MTRR for WC and using /dev/mem or resourceX under /sys)
Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: NIngo Molnar <mingo@elte.hu>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      de33c442
  59. 21 4月, 2008 1 次提交
  61. 17 4月, 2008 2 次提交
  63. 05 2月, 2008 1 次提交
    • D
      intel-agp: add chipset flushing support · 6c00a61e
      由 Dave Airlie 提交于 
      This adds support for flushing the chipsets on the 915, 945, 965 and G33
families of Intel chips.

The BIOS doesn't seem to always allocate the BAR on the 965 chipsets
so I have to use pci resource code to create a resource

It adds an export for pcibios_align_resource.
      6c00a61e
  65. 13 10月, 2007 2 次提交