- 13 2月, 2013 6 次提交
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由 Po Liu 提交于
This facilitates getting the physical address of the SEC node. Signed-off-by: NLiu po <po.liu@freescale.com> Reviewed-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
Fix and/or improve the compatible strings of the PCI device tree nodes for some Freescale SOCs. This fixes some issues and improves consistency among the SOCs. Specifically: 1) The P1022 has a v1 PCIe controller, so the compatible property should just say "fsl,mpc8548-pcie". U-Boot does not look for "fsl,p1022-pcie", so it wasn't fixing up the node. 2) The P4080 has a v2.1 PCIe controller, so add that version-specific string to the device tree. Update the kernel to also look for that string. Currently, the kernel looks for "fsl,p4080-pcie" specifically, but eventually that check should be deleted. 3) The P1010 device tree claims compatibility with v2.2 and v2.3, but that's redundant. No other device tree does this. Remove the v2.2 string. 4) The kernel looks for both "fsl,p1023-pcie" and "fsl,qoriq-pcie-v2.2", even though the P1023 device trees has always included both strings. Remove the search for "fsl,p1023-pcie". Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
The PAMU caches use the LIODNs to determine which cache lines hold the entries for the corresponding LIODs. The LIODNs must therefore be carefully assigned to avoid cache thrashing -- two active LIODs with LIODNs that put them in the same cache line. Currently, LIODNs are statically assigned by U-Boot, but this has limitations. LIODNs are assigned even for devices that may be disabled or unused by the kernel. Static assignments also do not allow for device drivers which may know which LIODs can be used simultaneously. In other words, we really should assign LIODNs dynamically in Linux. To do that, we need to describe the PAMU device and cache topologies in the device trees. Signed-off-by: NTimur Tabi <timur@freescale.com> Acked-by: NStuart Yoder <stuart.yoder@freescale.com> Acked-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Paul Gortmaker 提交于
By moving the two JP12 jumpers 90 degrees, and switching the setting of SW2.8, the sbc8548 can be configured to boot off the alternate 64MB SODIMM, which when populated with u-boot can be a handy recovery option, in case the u-boot in the 8MB soldered on flash gets corrupted. Here we add an alternate dts file to match that configuration. To better highlight the differences, the output from the u-boot "fli" command is shown for the normal configuration and then the alternate configuration. Normal: ----------------------- Bank # 1: CFI conformant flash (8 x 8) Size: 8 MB in 64 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x17 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 2 ms, buffer size: 32 bytes Sector Start Addresses: FF800000 E FF820000 E FF840000 E FF860000 E FF880000 E [...] FFEE0000 E FFF00000 E FFF20000 E FFF40000 E FFF60000 E FFF80000 FFFA0000 RO FFFC0000 RO FFFE0000 RO Bank # 2: CFI conformant flash (32 x 8) Size: 64 MB in 128 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x18 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 2 ms, buffer size: 32 bytes Sector Start Addresses: EC000000 E EC080000 E EC100000 E EC180000 E EC200000 E [...] EFC00000 E EFC80000 E EFD00000 E EFD80000 E EFE00000 E EFE80000 E EFF00000 EFF80000 ----------------------- Alternate: ----------------------- Bank # 1: CFI conformant flash (32 x 8) Size: 64 MB in 128 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x18 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 2 ms, buffer size: 32 bytes Sector Start Addresses: FC000000 E FC080000 E FC100000 E FC180000 E FC200000 E [...] FFC00000 E FFC80000 E FFD00000 E FFD80000 E FFE00000 E FFE80000 E FFF00000 RO FFF80000 RO Bank # 2: CFI conformant flash (8 x 8) Size: 8 MB in 64 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x17 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 2 ms, buffer size: 32 bytes Sector Start Addresses: EF800000 E EF820000 E EF840000 E EF860000 E EF880000 E [...] EFEE0000 E EFF00000 E EFF20000 E EFF40000 E EFF60000 E EFF80000 E EFFA0000 EFFC0000 EFFE0000 ----------------------- Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Paul Gortmaker 提交于
The original memory map for the sbc8548 had the 64MB SODIMM flash device misaligned by 8MB to allow a window of address space for the soldered on 8MB device -- i.e. start end CS<n> width Desc. ---------------------------------------------------------- fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) However, if we want to change the configuration so that it boots off the 64MB flash, it is in turn then aligned with a 64MB boundary, starting at fc00_0000 (and the 8MB @ fb80_0000 -> fbff_ffff). This makes for complicated updates, since what is the beginning of the physical device is 8MB into its address space in the default configuration shown above. This issue was fixed as of u-boot commit 3fd673cf363bc86ed42eff713d4 ("sbc8548: relocate 64MB user flash to sane boundary") -- in which the SODIMM was mapped to ec00_0000 (natively aligned under efff_ffff) and so when JP12/SW2.8 are switched, it will be a a simple 0xec --> 0xfc mapping between the two instances. Here we make the associated changes in the localbus flash memory map in the dts file: indicating the 64MB device starts at ec00_0000 and that the tail end of the 64MB device (last 2 sectors) can contain a bootloader image. The partitions for both flash devices get a clean-up; there were non-meaningful assignments in there that probably originated from the MPC8548CDS on which the file was based on. Now there is just the categorization of free space and bootloader images. Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Paul Gortmaker 提交于
Updates to u-boot allow this board to boot off of either the 8MB soldered on flash, or the 64MB SODIMM flash. This is achieved by changing JP12 and SW2.8 which in turn swaps which flash device appears on /CS0 and /CS6 respectively. Since the flash devices are not the same size, this also changes the MTD memory map layout on the local bus. Here we split the common chunks out into a pre and post include, so they can be reused by an upcoming "alternative boot" dts file; leaving only the local bus chunk behind. No content changes are made at this point - it is just purely the move to using include files. Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 10 1月, 2013 2 次提交
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由 Gernot Vormayr 提交于
This adds the marvel phy which is present on the ml507 board. Without this ethtool causes kernel-oopses. Tested on ml507 board. Signed-off-by: NGernot Vormayr <gvormayr@gmail.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Vinh Nguyen Huu Tuong 提交于
This patch consists of: - Add driver for OCM component - Export OCM Information at /sys/kernel/debug/ppc4xx_ocm/info Signed-off-by: NVinh Nguyen Huu Tuong <vhtnguyen@apm.com> Acked-by: NJosh Boyer <jwboyer@gmail.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 07 12月, 2012 1 次提交
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由 Stefan Roese 提交于
This patch adds the MPC5200B based a3m071 board. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Signed-off-by: NAnatolij Gustschin <agust@denx.de>
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- 25 11月, 2012 1 次提交
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由 Xuelin Shi 提交于
The RaidEngine is a new Freescale hardware that used for parity computation offloading in RAID5/6. This patch adds the device node in device tree and related binding documentation. Signed-off-by: NHarninder Rai <harninder.rai@freescale.com> Signed-off-by: NNaveen Burmi <naveenburmi@freescale.com> Signed-off-by: NXuelin Shi <b29237@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 26 10月, 2012 2 次提交
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由 Anatolij Gustschin 提交于
The LPB FIFO interrupt is a peripheral interrupt, thus its L1 cell has to be 2 instead of 3. Fix it and while at it, move the lpbfifo node to the common dtsi file. This patch fixes the irqdomain warning: ... WARNING: at kernel/irq/irqdomain.c:766 Modules linked in: NIP: c00587fc LR: c0058e0c CTR: c0014e54 REGS: c7837c10 TRAP: 0700 Tainted: G W (3.7.0-rc1-00003-g6e51414) MSR: 00029032 <EE,ME,IR,DR,RI> CR: 82cd8322 XER: 00000000 TASK = c7834000[1] 'swapper' THREAD: c7836000 GPR00: 00000001 c7837cc0 c7834000 c7806080 000000d7 c7837d20 00000003 c7837cec GPR08: c7837ce8 00000000 00000000 00000008 82cd3342 00000000 c0003f88 00000000 GPR16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 c7850ec0 GPR24: c782b010 00000000 00000001 c7852900 00000003 c7df5be0 c7806080 000000d7 NIP [c00587fc] irq_linear_revmap+0x2c/0x4c LR [c0058e0c] irq_create_mapping+0x28/0x124 Reported-by: NStefan Roese <sr@denx.de> Signed-off-by: NAnatolij Gustschin <agust@denx.de>
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由 Eric Millbrandt 提交于
Add a node for the pcm030-audio-fabric ASoC driver Signed-off-by: NEric Millbrandt <emillbrandt@dekaresearch.com> Signed-off-by: NAnatolij Gustschin <agust@denx.de>
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- 14 9月, 2012 1 次提交
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由 Anatolij Gustschin 提交于
Add common o2d dtsi file to reuse it for other configurations. Add machine compatible string to mpc5200 simple platform file. Add dts files for O2D, O2I, O2MNT, O2DNT2, O2D300 and O3DNT boards. Signed-off-by: NAnatolij Gustschin <agust@denx.de>
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- 13 9月, 2012 10 次提交
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由 Shaohui Xie 提交于
Device node adt7461 was wrongly added in p5040ds.dts, it should be added into i2c instead of localbus, when build p5040ds.dtb, a warning will dump: Warning (reg_format): "reg" property in /localbus@ffe124000/nand@2,0/adt7461@4c has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1) This was introduced by: commit ea6b1ba692bcb5f6e39f409a78cf8b04fdf23baa Author: Jia Hongtao <B38951@freescale.com> Date: Tue Aug 28 10:00:55 2012 +0800 powerpc: add adt7461 thermal monitor support to applicable boards Add thermal monitor support to following boards: P1022DS, MPC8536DS, P2041RDB, P3041DS, P4080DS, P5020DS, P5040DS Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Wang Dongsheng 提交于
create partition table for norflash. Signed-off-by: NWang Dongsheng <Dongsheng.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Jia Hongtao 提交于
Add thermal monitor support to following boards: P1022DS, MPC8536DS, P2041RDB, P3041DS, P4080DS, P5020DS, P5040DS Signed-off-by: NJia Hongtao <B38951@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Olivia Yin 提交于
power-isa-version and power-isa-* are cpu node general properties defined in ePAPR. If the power-isa-version property exists, then for each category from the Categories section of Book I of the Power ISA version indicated, the existence of a property named power-isa-[CAT], where [CAT] is the abbreviated category name with all uppercase letters converted to lowercase, indicates that the category is supported by the implementation. This patch update all the e5500 platforms. Signed-off-by: NLiu Yu <yu.liu@freescale.com> Signed-off-by: NOlivia Yin <hong-hua.yin@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Olivia Yin 提交于
power-isa-version and power-isa-* are cpu node general properties defined in ePAPR. If the power-isa-version property exists, then for each category from the Categories section of Book I of the Power ISA version indicated, the existence of a property named power-isa-[CAT], where [CAT] is the abbreviated category name with all uppercase letters converted to lowercase, indicates that the category is supported by the implementation. The patch update all the e500mc platforms. Signed-off-by: NLiu Yu <yu.liu@freescale.com> Signed-off-by: NOlivia Yin <hong-hua.yin@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Olivia Yin 提交于
power-isa-version and power-isa-* are cpu node general properties defined in ePAPR. If the power-isa-version property exists, then for each category from the Categories section of Book I of the Power ISA version indicated, the existence of a property named power-isa-[CAT], where [CAT] is the abbreviated category name with all uppercase letters converted to lowercase, indicates that the category is supported by the implementation. The patch update all e500v2 platforms. Signed-off-by: NLiu Yu <yu.liu@freescale.com> Signed-off-by: NOlivia Yin <hong-hua.yin@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
The Freescale / iVeia P1022RDK reference board is a small-factor board with a Freescale P1022 SOC. It includes: 1) 512 MB 64-bit DDR3-800 (max) memory 2) 8MB SPI serial flash memory for boot loader 3) Bootable 4-bit SD/MMC port 4) Two 10/100/1000 Ethernet connectors 5) One SATA port 6) Two USB ports 7) One PCIe x4 slot 8) DVI video connector 9) Audio input and output jacks, powered by a Wolfson WM8960 codec. Unlike the P1022DS, the P1022RDK does not have any localbus devices, presumably because of the localbus / DIU multiplexing restriction of the P1022 SOC. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which is similar to the P5020DS. Features of the P5040 are listed below, but not all of these features (e.g. DPAA networking) are currently supported. Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kim Phillips 提交于
Add device tree (dtsi) files for the Freescale P5040 SOC. Since this SOC introduces SEC v5.2, add the dtsi file for that also. Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
We only need two examples of CAMP device trees in the upstream kernel. Co-operative Asymmetric Multi-Processing (CAMP) is a technique where two or more operating systems (typically multiple copies of the same Linux kernel) are loaded into memory, and each kernel is given a subset of the available cores to execute on. For example, on a four-core system, one kernel runs on cores 0 and 1, and the other runs on cores 2 and 3. The devices are also partitioned among the operating systems, and this is done with customized device trees. Each kernel gets its own device tree that has only the devices that it should know about. Unfortunately, this approach is very hackish. The kernels are trusted to only access devices in their respective device trees, and the partitioning only works for devices that can be handled. Crafting the device trees is a tricky process, and getting U-Boot to load and start all kernels is cumbersome. But most importantly, each CAMP setup is very application-specific, since the actual partitioning of resources is done in the DTS by the system designer. Therefore, it doesn't make a lot of sense to have a lot of CAMP device trees, since we only expect them to be used as examples. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 07 9月, 2012 1 次提交
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由 Matthew McClintock 提交于
Several files in obj-plat depend on libfdt header file. Sometimes when building one can see the following issue. This patch adds libfdt as dependency to those object files | In file included from arch/powerpc/boot/treeboot-iss4xx.c:33:0: | arch/powerpc/boot/libfdt.h:854:1: error: unterminated comment | In file included from arch/powerpc/boot/treeboot-iss4xx.c:33:0: | arch/powerpc/boot/libfdt.h:1:0: error: unterminated #ifndef | BOOTCC arch/powerpc/boot/inffast.o | make[1]: *** [arch/powerpc/boot/treeboot-iss4xx.o] Error 1 | make[1]: *** Waiting for unfinished jobs.... | BOOTCC arch/powerpc/boot/inflate.o | make: *** [uImage] Error 2 | ERROR: oe_runmake failed | ERROR: Function failed: do_compile (see /srv/home/pokybuild/yocto-autobuilder/yocto-slave/p1022ds/build/build/tmp/work/p1022ds-poky-linux-gnuspe/linux-qoriq-sdk-3.0.34-r5/temp/log.do_compile.2167 for further information) NOTE: recipe linux-qoriq-sdk-3.0.34-r5: task do_compile: Failed Signed-off-by: NMatthew McClintock <msm@freescale.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 01 9月, 2012 1 次提交
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由 Paul Bolle 提交于
Commit 4f3865fb ("zlib_inflate: Upgrade library code to a recent version") removed infblock.c, infblock.h, infcodes.c, and infcodes.h from the tree. Remove their entries in powerpc's .gitignore file too. Signed-off-by: NPaul Bolle <pebolle@tiscali.nl> Signed-off-by: NJiri Kosina <jkosina@suse.cz>
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- 10 8月, 2012 1 次提交
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由 Shengzhou Liu 提交于
Add the missing usb controller version info and port0, which is required during setup usb phy. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 26 7月, 2012 2 次提交
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由 Shaohui Xie 提交于
Default CoreNet Coherency Bus (CCB) frequency on P3041 is 750MHz, but espi cannot work at 40MHz with this CCB frequency, so we need to slow down the clock rate of espi to 35MHz to make it work stable at the CCB frequency. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Tang Yuantian 提交于
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 12 7月, 2012 1 次提交
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由 Jia Hongtao 提交于
In SGMII riser card different PHY chip are used with different external IRQ from eTSEC. To support PHY link state auto detect in SGMII mode we should add another group of PHY nodes for SGMII mode. For MPC8572DS IRQ6 is used for PHY0~PHY1, IRQ7 is used for PHY2~PHY3. For MPC8544DS and MPC8536DS IRQ6 is used for PHY0~PHY1. For P2020DS IRQ5 is used for PHY1~PHY2. Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NJia Hongtao <B38951@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 11 7月, 2012 1 次提交
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由 Xu Jiucheng 提交于
The board is really P1021RDB-PC, so rename from p1021rdb.* to p1021rdb-pc.* Signed-off-by: NXu Jiucheng <Jiucheng.Xu@freescale.com> Signed-off-by: NMatthew McClintock <msm@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 10 7月, 2012 10 次提交
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由 Zhicheng Fan 提交于
Add device tree nodes to enable ucc uart support on P1025RDB. Signed-off-by: NZhicheng Fan <B32736@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Jia Hongtao 提交于
With 2-cell format interrupts of MSI PCIe ethernet card can not work. Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NJia Hongtao <B38951@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Jia Hongtao 提交于
The issue log on core1 is: root@mpc8572ds:~# ifconfig eth0 10.192.208.244 net eth0: could not attach to PHY SIOCSIFFLAGS: No such device To attach PHY node mdio@24520 should not be disabled in dts of core1. Because all PHYs are controlled through this node as follows: mdio@24520 { phy0: ethernet-phy@0 { interrupts = <10 1 0 0>; reg = <0x0>; }; phy1: ethernet-phy@1 { interrupts = <10 1 0 0>; reg = <0x1>; }; phy2: ethernet-phy@2 { interrupts = <10 1 0 0>; reg = <0x2>; }; phy3: ethernet-phy@3 { interrupts = <10 1 0 0>; reg = <0x3>; }; tbi0: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NJia Hongtao <B38951@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Prabhakar Kushwaha 提交于
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The BSC9131 is integrated SoC that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. BSC9131RDB Overview ---------------------- BSC9131 SoC 1Gbyte DDR3 (on board DDR) 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory USB-ULPI eTSEC1: Connected to RGMII PHY eTSEC2: Connected to RGMII PHY DUART interface: supports one UARTs up to 115200 bps for console display Linux runs on e500v2 core and access some DSP peripherals like AIC Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: NAkhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NRajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
This reverts commit 96cc017c. The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
In order to enable the DIU video controller on the P1022DS, the FPGA needs to be switched to "indirect mode", where the localbus is disabled and the FPGA is accessed via writes to localbus chip select signals CS0 and CS1. To obtain the address of CS0 and CS1, the platform driver uses an "indirect pixis mode" device tree node. This node assumes that the localbus 'ranges' property is sorted in chip-select order. That is, reg value 0 maps to CS0, reg value 1 maps to CS1, etc. This is how the 'ranges' property is supposed to be arranged. Unfortunately, the 'ranges' property is often mis-arranged, and not just on the P1022DS. Linux normally does not care, since it does not program the localbus. But the indirect-mode code on the P1022DS does care. The "proper" fix is to have U-Boot fix the 'ranges' property, but this would be too cumbersome. The names and 'reg' properties of all the localbus devices would also need to be updated, and determining which localbus device maps to which chip select is board-specific. Instead, we determine the CS0/CS1 base addresses the same way that U-boot does -- by reading the BRx registers directly and mapping them to physical addresses. This code is simpler and more reliable, and it does not require a U-boot or device tree change. Since the indirect pixis device tree node is no longer needed, the node is deleted from the DTS. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Shaohui Xie 提交于
NAND on p2041 uses CS1 as chip select. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Paul Gortmaker 提交于
This reference board dates back to 2004, and is largely a legacy EOL product. The MPC8560 is a pre e500v2 CPU. The SBC8548 is a more modern, better e500v2 target for people to use as a reference board with today's kernels, should they require one. Removing support for it will also allow us to remove some sbc8560 specific quirk handling in 8250 UART code, and some MTD mapping support. Cc: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Tang Yuantian 提交于
Signed-off-by: NJin Qing <b24347@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Gustavo Zacarias 提交于
Add EEPROM to the P1010RDB device tree. The 24c01 acts as a memory SPD so it shouldn't be overwritten without care. The 24c256 is a general purpose memory. Signed-off-by: NGustavo Zacarias <gustavo@zacarias.com.ar> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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