1. 30 1月, 2016 1 次提交
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  20. 26 10月, 2014 1 次提交
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    • A
      iio:adc: at91 requires the input subsystem · 758ee467
      Arnd Bergmann 提交于
      Building the at91 adc driver with CONFIG_INPUT disabled results in this
      build error:
      
      ERROR: "input_event" [drivers/iio/adc/at91_adc.ko] undefined!
      ERROR: "input_unregister_device" [drivers/iio/adc/at91_adc.ko] undefined!
      ERROR: "input_free_device" [drivers/iio/adc/at91_adc.ko] undefined!
      ERROR: "input_register_device" [drivers/iio/adc/at91_adc.ko] undefined!
      ERROR: "input_set_abs_params" [drivers/iio/adc/at91_adc.ko] undefined!
      ERROR: "input_allocate_device" [drivers/iio/adc/at91_adc.ko] undefined!
      
      To make sure we can build random configurations, this adds a Kconfig
      dependency on CONFIG_INPUT, as we do for other similar drivers.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Cc: linux-iio@vger.kernel.org
      Cc: Josh Wu <josh.wu@atmel.com>
      Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
      Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
      Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      758ee467
  27. 26 4月, 2014 1 次提交
  28. 12 4月, 2014 1 次提交
  29. 18 3月, 2014 1 次提交
  30. 17 3月, 2014 2 次提交
  31. 02 3月, 2014 1 次提交
    • L
      iio:adc: Add Xilinx XADC driver · bdc8cda1
      Lars-Peter Clausen 提交于
      The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx.
      The XADC has a DRP interface for communication. Currently two different
      frontends for the DRP interface exist. One that is only available on the ZYNQ
      family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
      on all series 7 platforms and is a softmacro with a AXI interface. This driver
      supports both interfaces and internally has a small abstraction layer that hides
      the specifics of these interfaces from the main driver logic.
      
      The ADC has a couple of internal channels which are used for voltage and
      temperature monitoring of the FPGA as well as one primary and up to 16 channels
      auxiliary channels for measuring external voltages. The external auxiliary
      channels can either be directly connected each to one physical pin on the FPGA
      or they can make use of an external multiplexer which is responsible for
      multiplexing the external signals onto one pair of physical pins.
      
      The voltage and temperature monitoring channels also have an event capability
      which allows to generate a interrupt when their value falls below or raises
      above a set threshold.
      
      Buffered sampling mode is supported by the driver, but only for AXI-XADC since
      the ZYNQ XADC interface does not have capabilities for supporting buffer mode
      (no end-of-conversion interrupt). If buffered mode is supported the driver will
      register two triggers. One "xadc-samplerate" trigger which will generate samples
      with the configured samplerate. And one "xadc-convst" trigger which will
      generate one sample each time the CONVST (conversion start) signal is asserted.
      Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
      Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      bdc8cda1
  32. 01 3月, 2014 1 次提交
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  34. 28 9月, 2013 1 次提交
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  36. 08 9月, 2013 1 次提交