The ColdFire 5249 CPU has a second (compleletly different) interrupt
controller. It is the only ColdFire CPU that has this type. It controlls
GPIO interrupts amongst a number of interrupts from other internal
peripherals. Add support code for it.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The recent changes to the old ColdFire interrupt controller code means
we no longer need to manually unmask the timer interrupt. That is now
done in the interrupt controller code proper.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The older simple ColdFire interrupt controller has no one-to-one mapping
of interrupt numbers to bits in the interrupt mask register. Create a
mapping array that each ColdFire CPU type can populate with its available
interrupts and the bits that each use in the interrupt mask register.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The newer ColdFire 532x family of CPU's uses the old timer, but has a
newer interrupt controller. It doesn't need the special timer setup
that was required when using the older interrupt controller. Remove the
dead timer irq and level setting code, and define the hard coded vector.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The ColdFire "timers" clock setup can be simplified. There is really no
need for the flexible per-platform setup code. The clock interrupt can be
hard defined per CPU platform (in CPU include files). This makes the
actual timer code simpler.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The external interrupts used on the old Coldfire parts with the old style
interrupt controller can be properly mask/unmasked in the interrupt
handling code.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Currently the code that supports setting the old style ColdFire interrupt
controller mask registers is macros in the include files of each of the
CPU types. Merge all these into a set of real masking functions in the
old Coldfire interrupt controller code proper. All the macros are basically
the same (excepting a register size difference on really early parts).
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Each of the ColdFire CPU platform code that used the old style interrupt
controller had its own copy of the mcf_autovector() function. They are all
the same, remove them all and create a single function in the common
coldfire/intc.c code.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Create an mcfintc.h include file with the definitions for the old style
ColdFire interrupt controller. They are only needed on CPU's that use
this old controller - so isolate them on their own.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The ColdFire intc-simr interrupt controller should mask off all
interrupt sources at init time. Doing it here instead of separately
in each platform setup.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

With fully implemented interrupt controller code we don't need to do
the custom interrupt setup for the timer device of the ColdFire 532x.
Remove that code.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

With proper interrupt controller code in place there is no need for
devices like the timers to have custom interrupt masking code.
Remove it (and the defines that go along with it).
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The new code for the interrupt controller in the ColdFire 520x takes
care of all the interrupt controller setup. No manual config of the
level registers (ICR) is required by the  platform device setup code.
So remove it.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Each different m68knommu CPU interrupt controller type has its own
interrupt controller data structures now. Remove the old, and now not
used, common irq structs and init code from here.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Define the interrupt controller structures along with the interrupt
controller code for the 68360 CPU. This brings the interrupt setup
and control into one place for this CPU family.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Define the interrupt controller structures along with the interrupt
controller code for the 68328 CPU family. This brings the interrupt
setup and control into one place for this CPU family.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The old ColdFire CPU's (5206, 5307, 5407, 5249 etc) use a simple
interrupt controller. Use common setup code for them. This addition
means that all ColdFire CPU's now have some specific type of interrupt
controller code.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

With the common intc-simr interrupt controller code in place the ColdFire
532x family startup code can be greatly simplified. Remove all the
interrupt masking code, and the per-device interrupt config here.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The ColdFire 532x family of parts uses 2 of the same INTC interrupt
controlers used in the ColdFire 520x family. So modify the code to
support both parts. The extra code for the second INTC controler in
the case of the 520x is easily optimized away to nothing.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

With the common intc-2 interrupt controller code in place the ColdFire
523x family startup code can be greatly simplified. Remove all the
interrupt masking code, and the per-device interrupt config here.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

With the common intc-2 interrupt controller code in place the ColdFire
528x family startup code can be greatly simplified. Remove all the
interrupt masking code, and the per-device interrupt config here.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

With the common intc-2 interrupt controller code in place the ColdFire
527x family startup code can be greatly simplified. Remove all the
interrupt masking code, and the per-device interrupt config here.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Create general interrupt controller code for the many ColdFire version 2
cores that use the two region INTC interrupt controller. This includes the
523x family, 5270, 5271, 5274, 5275, and the 528x families.

This code does proper masking and unmasking of interrupts. With this in
place some of the driver hacks in place to support ColdFire interrupts
can finally go away.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

With general interrupt controller code in place we don't need specific
unmasking code for the internal ColdFire 520x UARTs or ethernet (FEC).
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Create general interrupt controller code for the ColdFire 520x family,
that does proper masking and unmasking of interrupts. With this in
place some of the driver hacks in place to support ColdFire interrupts
can finally go away.

Within the ColdFire family there is a variety of different interrupt
controllers in use. Some are used on multiple parts, some on only one.
There is quite some differences in some varients, so much so that
common code for all ColdFire parts would be impossible.

This commit introduces code to support one of the newer interrupt
controllers in the ColdFire 5208 and 5207 parts. It has very simple
mask and unmask operations, so is one of the easiest to support.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Change C99 style comments to traditional K&R style.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The non-mmu version of dma.h contains a lot of ColdFire specific DMA
support, but also all of the base m68k support. So use the non-mmu
version of dma.h for all.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The mmu and non-mmu versions of checksum.h are mostly the same,
merge them.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

It is reasonably strait forward to merge the mmu and non-mmu versions
of irq.h. Most of the defines and structs are not needed on non-mmu.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The mmu and non-mmu versions of processor.h have a lot of common code.
This is a strait forward merge. start_thread() could be improved, but
that is not quite as strait forward, leaving for a follow on change.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Signed-off-by: NChristoph Hellwig <hch@lst.de>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Signed-off-by: NJoe Perches <joe@perches.com>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The definition of MCFSIM_PADDR and MCFSIM_PADAT now has MCF_BAR already added in.
Signed-off-by: NSteven King <sfking@fdwdc.com>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Add support for the 5407.
Signed-off-by: NSteven King <sfking@fdwdc.com>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Add support for the 532x.
Signed-off-by: NSteven King <sfking@fdwdc.com>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Add support for the 5307.
Signed-off-by: NSteven King <sfking@fdwdc.com>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Add support for the 528x.
Signed-off-by: NSteven King <sfking@fdwdc.com>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Add support for the 5272.
Signed-off-by: NSteven King <sfking@fdwdc.com>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Add support for the 5271 & 5275.
Signed-off-by: NSteven King <sfking@fdwdc.com>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>