1. 10 1月, 2018 1 次提交
    • T
      drm/tegra: sor: Fix hang on Tegra124 eDP · d780537f
      Thierry Reding 提交于
      The SOR0 found on Tegra124 and Tegra210 only supports eDP and LVDS and
      therefore has a slightly different clock tree than the SOR1 which does
      not support eDP, but HDMI and DP instead.
      
      Commit e1335e2f ("drm/tegra: sor: Reimplement pad clock") breaks
      setups with eDP because the sor->clk_out clock is uninitialized and
      therefore setting the parent clock (either the safe clock or either of
      the display PLLs) fails, which can cause hangs later on since there is
      no clock driving the module.
      
      Fix this by falling back to the module clock for sor->clk_out on those
      setups. This guarantees that the module will always be clocked by an
      enabled clock and hence prevents those hangs.
      
      Fixes: e1335e2f ("drm/tegra: sor: Reimplement pad clock")
      Reported-by: NGuillaume Tucker <guillaume.tucker@collabora.com>
      Tested-by: NJon Hunter <jonathanh@nvidia.com>
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      d780537f
  2. 09 1月, 2018 3 次提交
  3. 08 1月, 2018 5 次提交
  4. 07 1月, 2018 6 次提交
  5. 06 1月, 2018 15 次提交
  6. 05 1月, 2018 10 次提交