1. 12 5月, 2016 5 次提交
  2. 11 5月, 2016 16 次提交
  3. 02 5月, 2016 1 次提交
  4. 14 4月, 2016 1 次提交
    • A
      dmaengine: dw: rename masters to reflect actual topology · c422025c
      Andy Shevchenko 提交于
      The source and destination masters are reflecting buses or their layers to
      where the different devices can be connected. The patch changes the master
      names to reflect which one is related to which independently on the transfer
      direction.
      
      The outcome of the change is that the memory data width is now always limited
      by a data width of the master which is dedicated to communicate to memory.
      
      The patch will not break anything since all current users have the same data
      width for all masters. Though it would be nice to revisit avr32 platforms to
      check what is the actual hardware topology in use there. It seems that it has
      one bus and two masters on it as stated by Table 8-2, that's why everything
      works independently on the master in use. The purpose of the sequential patch
      is to fix the driver for configuration of more than one bus.
      
      The change is done in the assumption that src_master and dst_master are
      reflecting a connection to the memory and peripheral correspondently on avr32
      and otherwise on the rest.
      Acked-by: NHans-Christian Egtvedt <egtvedt@samfundet.no>
      Acked-by: NMark Brown <broonie@kernel.org>
      Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      c422025c
  5. 18 3月, 2016 1 次提交
  6. 12 3月, 2016 2 次提交
  7. 04 3月, 2016 1 次提交
  8. 01 3月, 2016 2 次提交
  9. 26 2月, 2016 2 次提交
    • O
      sata_via: Implement hotplug for VT6421 · 57e5568f
      Ondrej Zary 提交于
      Enable IRQ on hotplug and add an interrupt handler to handle it.
      
      This allows hotplug to work:
      ata5: exception Emask 0x10 SAct 0x0 SErr 0x70000 action 0xe frozen
      ata5: SError: { PHYRdyChg PHYInt CommWake }
      ata5: hard resetting link
      ata5: SATA link up 1.5 Gbps (SStatus 113 SControl 310)
      ata5.00: LPM support broken, forcing max_power
      ata5.00: ATA-7: WDC WD800JD-75MSA3, 10.01E04, max UDMA/133
      ata5.00: 156250000 sectors, multi 0: LBA48 NCQ (depth 0/32)
      ata5.00: LPM support broken, forcing max_power
      ata5.00: configured for UDMA/133
      ata5: EH complete
      scsi 4:0:0:0: Direct-Access     ATA      WDC WD800JD-75MS 1E04 PQ: 0 ANSI: 5
      sd 4:0:0:0: [sdb] 156250000 512-byte logical blocks: (80.0 GB/74.5 GiB)
      sd 4:0:0:0: [sdb] Write Protect is off
      sd 4:0:0:0: [sdb] Mode Sense: 00 3a 00 00
      sd 4:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
      sd 4:0:0:0: Attached scsi generic sg1 type 0
      sd 4:0:0:0: [sdb] Attached SCSI disk
      
      And also hot unplug:
      ata5: exception Emask 0x10 SAct 0x0 SErr 0x1b0000 action 0xe frozen
      ata5: SError: { PHYRdyChg PHYInt 10B8B Dispar }
      ata5: hard resetting link
      ata5: SATA link down (SStatus 0 SControl 310)
      ata5: hard resetting link
      ata5: SATA link down (SStatus 0 SControl 310)
      ata5: hard resetting link
      ata5: SATA link down (SStatus 0 SControl 310)
      ata5.00: disabled
      ata5: EH complete
      ata5.00: detaching (SCSI 4:0:0:0)
      sd 4:0:0:0: [sdb] Synchronizing SCSI cache
      sd 4:0:0:0: [sdb] Synchronize Cache(10) failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK
      sd 4:0:0:0: [sdb] Stopping disk
      sd 4:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK
      Signed-off-by: NOndrej Zary <linux@rainbow-software.org>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      57e5568f
    • O
      sata_via: Apply WD workaround only when needed on VT6421 · 44a9b494
      Ondrej Zary 提交于
      Currently, workaround for broken WD drives is applied always, slowing
      down all drives. And it has a bug - it's not applied after resume.
      
      Apply the workaround only if the error really appears
      (SErr == 0x1000500). This allows unaffected drives to run at full speed
      (provided that no affected drive is connected to the controller).
      Also make sure the workaround is re-applied on resume.
      
      Tested on VT6421.
      As SCR registers access is known to cause problems on VT6420 (and I
      don't have it to test), keep the workaround applied always on VT6420.
      
      Unaffected drive (Hitachi HDS721680PLA380):
      Before:
      $ hdparm -t --direct /dev/sdb
      /dev/sdb:
       Timing O_DIRECT disk reads: 160 MB in  3.01 seconds =  53.16 MB/sec
      
      After:
      $ hdparm -t --direct /dev/sdb
      /dev/sdb:
       Timing O_DIRECT disk reads: 200 MB in  3.01 seconds =  66.47 MB/sec
      
      Affected drive (WDC WD5003ABYX-18WERA0):
      Before:
      $ hdparm -t --direct /dev/sda
      
      /dev/sda:
       Timing O_DIRECT disk reads: 180 MB in  3.02 seconds =  59.51 MB/sec
      
      After:
      $ hdparm -t --direct /dev/sdb
      /dev/sdb:
       Timing O_DIRECT disk reads: 156 MB in  3.03 seconds =  51.48 MB/sec
      $ hdparm -t --direct /dev/sdb
      /dev/sdb:
       Timing O_DIRECT disk reads: 180 MB in  3.02 seconds =  59.64 MB/sec
      
      The first hdparm is slower because of the error:
      [   50.408042] ata5: Incompatible drive: enabling workaround. This slows down transfer rate to ~60 MB/s
      [   50.728052] ata5: SATA link up 1.5 Gbps (SStatus 113 SControl 310)
      [   50.744834] ata5.00: configured for UDMA/133
      Signed-off-by: NOndrej Zary <linux@rainbow-software.org>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      44a9b494
  10. 19 2月, 2016 8 次提交
  11. 16 2月, 2016 1 次提交