- 23 4月, 2013 1 次提交
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由 Rafał Miłecki 提交于
After comparing writes to registers at 0x000, 0x400 and 0x800 it seems there are many very similar writes. So 0x000 offset is not for accessing something totally different, but probably just the first out of three cores. Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
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- 30 6月, 2011 1 次提交
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由 Rafał Miłecki 提交于
Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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- 23 6月, 2011 2 次提交
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由 Rafał Miłecki 提交于
Switching channel happens after specific SHM write to B43_SHM_SH_CHAN. This is the way we found it in BCM4331 MMIO dumps. By comparing with N-PHY code we noticed there is routing used for SYN and TX/RX. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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由 Rafał Miłecki 提交于
Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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