1. 25 2月, 2012 1 次提交
  2. 10 3月, 2011 1 次提交
  3. 04 2月, 2011 1 次提交
  4. 22 12月, 2010 2 次提交
  5. 28 9月, 2010 1 次提交
    • J
      omap3: Prevent SDRC deadlock when L3 is changing frequency · a3fed9bc
      Jon Hunter 提交于
      When changing the L3 clock frequency, the CPU is executing from internal RAM
      and the SDRC clock is disabled. During this time accesses made to external
      DDR are stalled. If the ARM subsystem attempts to access the DDR while the
      SDRC clock is disabled this will stall the CPU until the access to the SDRC
      timeouts. A timeout on the SDRC should never occur. Once a timeout occurs all
      the following accesses will be aborted and the DDR is no longer accessible.
      
      Although the code being executed in the internal RAM does not directly access
      the DDR, it was found that the branch prediction logic in the CPU may cause
      the CPU to prefetch code from a DDR location while the SDRC clock is disabled.
      This was causing an SDRC timeout which resulted in a system hang.
      
      This patch fixes this problem by ensuring the branch prediction logic is
      disabled while changing the L3 clock frequency. The branch prediction logic
      is disabled by clearing the Z-bit in the ARM CTRL register.
      
      Disabling the branch prediction logic does not have any noticable impact
      on the execution time of this code section. The hardware observability
      signals were used to monitor the sdrc idle time with and without this
      patch when operating at different CPU frequencies (150MHz, 500MHz and
      600MHz) and the total sdrc idle time when changing frequenct was in
      the range of 9-11us. This was measured on an omap3430 SDP running the
      omapzoom p-android-omap-2.6.29 branch.
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
      Cc: Richard Woodruff <r-woodruff2@ti.com>
      Cc: Tony Lindgren <tony@atomide.com>
      a3fed9bc
  6. 12 12月, 2009 1 次提交
    • P
      OMAP3: SDRC: Place SDRC AC timing and MR changes in CORE DVFS SRAM code behind Kconfig · 18862cbe
      Paul Walmsley 提交于
      The code that reprograms the SDRC memory controller during CORE DVFS,
      mach-omap2/sram34xx.S:omap3_sram_configure_core_dpll(), does not
      ensure that all L3 initiators are prevented from accessing the SDRAM
      before modifying the SDRC AC timing and MR registers.  This can cause
      memory to be corrupted or cause the SDRC to enter an unpredictable
      state.  This patch places that code behind a Kconfig option,
      CONFIG_OMAP3_SDRC_AC_TIMING for now, and adds a note explaining what
      is going on.  Ideally the code can be added back in once supporting
      code is present to ensure that other initiators aren't touching the
      SDRAM.  At the very least, these registers should be reprogrammable
      during kernel init to deal with buggy bootloaders.  Users who know
      that all other system initiators will not be touching the SDRAM can
      also re-enable this Kconfig option.
      
      This is a modification of a patch originally written by Rajendra Nayak
      <rnayak@ti.com> (the original is at http://patchwork.kernel.org/patch/51927/).
      Rather than removing the code completely, this patch just comments it out.
      
      Thanks to Benoît Cousson <b-cousson@ti.com> and Christophe Sucur
      <c-sucur@ti.com> for explaining the technical basis for this and for
      explaining what can be done to make this path work in future code.
      Thanks to Richard Woodruff <r-woodruff2@ti.com>, Nishanth Menon
      <nm@ti.com>, and Olof Johansson <olof@lixom.net> for their comments.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      Cc: Christophe Sucur <c-sucur@ti.com>
      Cc: Benoît Cousson <b-cousson@ti.com>
      Cc: Richard Woodruff <r-woodruff2@ti.com>
      Cc: Nishanth Menon <nm@ti.com>
      Cc: Olof Johansson <olof@lixom.net>
      18862cbe
  7. 25 7月, 2009 4 次提交
    • R
      OMAP3 SDRC: Move the clk stabilization delay to the right place · df56556e
      Rajendra Nayak 提交于
      The clock stabilization delay post a M2 divider change is needed
      even before a SDRC interface clock re-enable and not only before
      jumping back to SDRAM.
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      df56556e
    • R
      OMAP3 SDRC: Fix freeze when scaling CORE dpll to < 83Mhz · 8ff120e5
      Rajendra Nayak 提交于
      This patch fixes a bug in the CORE dpll scaling sequence which was
      errouneously clearing some bits in the SDRC DLLA CTRL register and
      hence causing a freeze.  The issue was observed only on platforms
      which scale CORE dpll to < 83Mhz and hence program the DLL in fixed
      delay mode.
      
      Issue reported by Limei Wang <E12499@motorola.com>, with debugging
      assistance from Richard Woodruff <r-woodruff2@ti.com> and Girish
      Ghongdemath <girishsg@ti.com>.
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      Cc: Limei Wang <E12499@motorola.com>
      Cc: Richard Woodruff <r-woodruff2@ti.com>
      Cc: Girish Ghongdemath <girishsg@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      [paul@pwsan.com: updated patch description to include collaboration credits]
      8ff120e5
    • P
      OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on boot · 75f251e3
      Paul Walmsley 提交于
      Stop setting SDRC_POWER.PWDENA on boot.  There is a nasty erratum
      (34xx erratum 1.150) that can cause memory corruption if PWDENA is
      enabled.
      
      Based originally on a patch from Samu P. Onkalo <samu.p.onkalo@nokia.com>.
      
      Tested on BeagleBoard rev C2.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Samu P. Onkalo <samu.p.onkalo@nokia.com>
      75f251e3
    • J
      OMAP3 SDRC: add support for 2 SDRAM chip selects · 58cda884
      Jean Pihet 提交于
      Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2
      SDRAM parts connected to the SDRC.
      
      This patch adds the following:
      - add a new argument of type omap_sdrc_params struct*
      to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
      - adapted the OMAP boards files to the new prototype of
      omap2_init_common_hw
      - add the SDRC 2nd CS registers offsets defines
      - adapt the sram sleep code to configure the SDRC for the 2nd CS
      
      Note: If the 2nd param to omap2_init_common_hw is NULL, then the
      parameters are not programmed into the SDRC CS1 registers
      
      Tested on 3430 SDP and Beagleboard rev C2 and B5, with
      suspend/resume and frequency changes (cpufreq).
      Signed-off-by: NJean Pihet <jpihet@mvista.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      58cda884
  8. 20 6月, 2009 7 次提交
  9. 13 5月, 2009 5 次提交
    • P
      OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz · 4519c2bf
      Paul Walmsley 提交于
      According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the
      DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC
      clock frequency from 83MHz to 166MHz.  CDP code unconditionally
      unlocked the DLL whenever shifting to a lower SDRC speed, but this
      seems unnecessary and error-prone, as the DLL is no longer able to
      compensate for process, voltage, and temperature variations.  Instead,
      only unlock the DLL when the SDRC clock rate would be less than 83MHz.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      4519c2bf
    • P
      OMAP3 SRAM: renumber registers to make space for argument passing · b2abb271
      Paul Walmsley 提交于
      Renumber registers in omap3_sram_configure_core_dpll() assembly code to
      make space for additional parameters.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      b2abb271
    • P
      OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change · fa0406a8
      Paul Walmsley 提交于
      Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh
      mode.  This prevents the SDRC from attempting to power off the SDRAM,
      which can cause the system to hang.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      fa0406a8
    • P
      OMAP3 clock: add interconnect barriers to CORE DPLL M2 change · d75d9e73
      Paul Walmsley 提交于
      Where necessary, add interconnect barriers to force posted writes to
      complete before continuing.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      d75d9e73
    • P
      OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpll · 69d4255b
      Paul Walmsley 提交于
      Add more barriers in the SRAM CORE DPLL M2 divider change code.
      
      - Add a DSB SY after the function's entry point to flush all cached
        and buffered writes and wait for the interconnect to claim that they
        have completed[1].  The idea here is to force all delayed write
        traffic going to the SDRAM to at least post to the L3 interconnect
        before continuing.  If these writes are allowed to occur after the
        SDRC is idled, the writes will not be acknowledged and the ARM will
        stall.
      
        Note that in this case, it does not matter if the writes actually
        complete to the SDRAM - it is only necessary for the writes to leave
        the ARM itself.  If the writes are posted by the interconnect when
        the SDRC goes into idle, the writes will be delayed until the SDRC
        returns from idle[2].  If the SDRC is in the middle of a write when
        it is requested to enter idle, the SDRC will not acknowledge the
        idle request until the writes complete to the SDRAM.[3]
      
        The old-style DMB in sdram_in_selfrefresh is now superfluous, so,
        remove it.
      
      - Add an ISB before the function's exit point to prevent the ARM from
        speculatively executing into SDRAM before the SDRAM is enabled[4].
      
      ...
      
      1. ARMv7 ARM (DDI 0406A) A3-47, A3-48.
      
      2. Private communication with Richard Woodruff <r-woodruff2@ti.com>.
      
      3. Private communication with Richard Woodruff <r-woodruff2@ti.com>.
      
      4. ARMv7 ARM (DDI 0406A) A3-48.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Richard Woodruff <r-woodruff2@ti.com>
      69d4255b
  10. 09 10月, 2008 1 次提交
    • S
      ARM: OMAP3: Add minimal omap3430 support · cc26b3b0
      Syed Mohammed, Khasim 提交于
      Add minimal omap3430 support based on earlier patches from
      Syed Mohammed Khasim. Also merge in omap34xx SRAM support
      from Karthik Dasu and use consistent naming for sram init
      functions.
      
      Also do following changes that make 34xx support usable:
      
      - Remove unused sram.c functions for 34xx
      
      - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally
        in entry-macro.S
      
      - Update mach-omap2/io.c to support 2420, 2430, and 34xx
      
      - Also merge in 34xx GPMC changes to add fields wr_access and
        wr_data_mux_bus from Adrian Hunter
      
      - Remove memory initialization call omap2_init_memory() until
        until more generic memory initialization patches are posted.
        It's OK to rely on bootloader initialization until then.
      Signed-off-by: NSyed Mohammed, Khasim <khasim@ti.com>
      Signed-off-by: Karthik Dasu<karthik-dp@ti.com>
      Signed-off-by: NAdrian Hunter <ext-adrian.hunter@nokia.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      
      
      
      cc26b3b0