1. 03 3月, 2012 2 次提交
  2. 27 2月, 2012 1 次提交
  3. 10 2月, 2012 1 次提交
  4. 03 2月, 2012 1 次提交
  5. 10 1月, 2012 2 次提交
  6. 03 1月, 2012 1 次提交
  7. 20 12月, 2011 1 次提交
  8. 19 12月, 2011 1 次提交
  9. 15 12月, 2011 1 次提交
  10. 09 12月, 2011 1 次提交
    • J
      ARM: OMAP1: Move dpll1 rates selection from config to runtime · 24ce2705
      Janusz Krzysztofik 提交于
      For still better multi-OMAP1 support, expand omap1_rate_table with flags
      for different SoC types and match them while selecting clock rates. The
      idea is stolen from current omap24xx clock rate selection algorithm.
      
      Since clkdev platform flag definitions are reused here, those had to be
      expanded with one extra entry for OMAP1710 subtype, as this is the only
      SoC for which we allow selection of the highest, 216 MHz rate.
      
      Once done, remove no longer needed clock rate configure time options.
      
      Tested on Amstrad Delta.
      Signed-off-by: NJanusz Krzysztofik <jkrzyszt@tis.icnet.pl>
      [tony@atomide.com: updated comments]
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      24ce2705
  11. 02 12月, 2011 1 次提交
    • J
      ARM: OMAP1: Remove unsafe clock values from omap1_defconfig · b29e2354
      Janusz Krzysztofik 提交于
      DPLL1 reprogramming to a different rate is actually blocked inside
      omap1_select_table_rate(), resulting in the defalut rate of 60 MHz
      always used instead of the one selected in .config. OTOH, in
      omap1_defconfig we currently rely on Kconfig options for the supported
      MHz rates in case of boards which boot with dpll1 not set correctly by
      their boot loaders.
      
      This means that before we allow for reprogramming of dpll1 rate, we
      should remove all unsafe clock selections from omap1_defconfig,
      otherwise it will stop booting on boards with imperfect boot loaders,
      as it would always try to change to 216MHz.
      
      Keep only one safe clock rate per each supported xtal frequency, i.e.
      60MHZ dpll1 for 12MHz xtal and 182MHz dpll1 for 13MHz xtal.
      
      BTW, this change goes into the direction of removing all OMAP1 clock
      rate options, planned for next merge window.
      Signed-off-by: NJanusz Krzysztofik <jkrzyszt@tis.icnet.pl>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      b29e2354
  12. 29 11月, 2011 2 次提交
  13. 24 11月, 2011 3 次提交
  14. 16 11月, 2011 1 次提交
  15. 12 11月, 2011 1 次提交
    • T
      ARM: OMAP: Fix reprogramming of dpll1 rate · e9b7086b
      Tony Lindgren 提交于
      Commit a66cb345 (ARM: OMAP: Map SRAM
      later on with ioremap_exec()) moved the SRAM init to happen later
      to remove a dependency to early SoC detection for map_io.
      
      This broke booting on some boards not using Kconfig option for
      OMAP_CLOCKS_SET_BY_BOOTLOADER as the dpll1 reprogramming would
      cause the following error:
      
      kernel BUG at arch/arm/plat-omap/sram.c:226!
      Internal error: Oops - undefined instruction: 0 [#1] PREEMPT
      Modules linked in:
      
      CPU: 0    Not tainted  (3.2.0-rc1-e3 #9)
      PC is at omap_sram_reprogram_clock+0x28/0x30
      LR is at omap1_select_table_rate+0x88/0xb4
      pc : [<c001b0c4>]    lr : [<c0019f54>]    psr: 600000d3
      sp : c035bf10  ip : c035bf20  fp : c035bf1c
      r10: c035bfd4  r9 : 54029252  r8 : c03f8120
      r7 : c0362b50  r6 : 00b71b00  r5 : c03873cc  r4 : c0362b40
      r3 : 00000000  r2 : c0362b40  r1 : 0000010a  r0 : 00002cb0
      Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
      Control: 0000317f  Table: 10004000  DAC: 00000017
      Process swapper (pid: 0, stack limit = 0xc035a270)
      Stack: (0xc035bf10 to 0xc035c000)
      bf00:                                     c035bf3c c035bf20 c0019f54 c001b0ac
      bf20: 00001000 00002cb3 00000004 c035ed4c c035bf74 c035bf40 c033ea24 c0019edc
      bf40: c02f526c 00000002 00000015 bc058c9b 93111a16 c035335c 02000000 c035ed4c
      bf60: c035ed4c c03f8120 c035bf84 c035bf78 c00194c4 c033e8ec c035bfc4 c035bf88
      bf80: c033bc24 c00194a0 c035bf90 c035bf98 00000000 00000000 00000000 00000000
      bfa0: 00000001 00000000 c0354678 c035ece4 10004000 103532f4 c035bff4 c035bfc8
      bfc0: c0338574 c033b598 00000000 00000000 00000000 c035467c 0000317d c035c03c
      bfe0: c0354678 c035ece4 00000000 c035bff8 10008040 c0338508 00000000 00000000
      Backtrace:
      [<c001b09c>] (omap_sram_reprogram_clock+0x0/0x30) from [<c0019f54>] (omap1_select_table_rate+0x88/0xb4)
      [<c0019ecc>] (omap1_select_table_rate+0x0/0xb4) from [<c033ea24>] (omap1_clk_init+0x148/0x334)
       r7:c035ed4c r6:00000004 r5:00002cb3 r4:00001000
      [<c033e8dc>] (omap1_clk_init+0x0/0x334) from [<c00194c4>] (omap1_init_early+0x34/0x48)
       r8:c03f8120 r7:c035ed4c r6:c035ed4c r5:02000000 r4:c035335c
      [<c0019490>] (omap1_init_early+0x0/0x48) from [<c033bc24>] (setup_arch+0x69c/0x79c)
      [<c033b588>] (setup_arch+0x0/0x79c) from [<c0338574>] (start_kernel+0x7c/0x2f4)
      [<c03384f8>] (start_kernel+0x0/0x2f4) from [<10008040>] (0x10008040)
       r7:c035ece4 r6:c0354678 r5:c035c03c r4:0000317d
      Code: 0a000002 e1a0e00f e12fff13 e89da800 (e7f001f2)
      
      Fix this by adding omap1_clk_late_init() that only reprograms dpll1
      if the bootloader rate is less than 60MHz. This also allows removing
      of the OMAP_CLOCKS_SET_BY_BOOTLOADER option.
      Reported-by: NAaro Koskinen <aaro.koskinen@iki.fi>
      Tested-by: NAaro Koskinen <aaro.koskinen@iki.fi>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      e9b7086b
  16. 11 11月, 2011 2 次提交
  17. 10 11月, 2011 1 次提交
  18. 06 11月, 2011 1 次提交
    • K
      ARM: EXYNOS: Add ARCH_EXYNOS and reorganize arch/arm/mach-exynos · 83014579
      Kukjin Kim 提交于
      The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has
      made for plaforms based on EXYNOS4 SoCs. But since upcoming
      Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most
      codes in current mach-exynos4, one mach-exynos directory will
      be used for them.
      
      This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos)
      but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to
      avoid changing in driver side.
      
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Russell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
      83014579
  19. 17 10月, 2011 1 次提交
    • L
      ARM: 7102/1: mach-integrator: update defconfig · a675002c
      Linus Walleij 提交于
      Update the Integrator defconfig with some sensible defaults:
      - Compile a combined image supporting Integrator/AP and
        Integrator/CP, with the core modules CM720, CM920, CM922,
        CM926, CM1020, CM1022 and CM1026 in a single image, this
        works just fine and gives some nice compilation coverage
      - NOHZ (tickless) and HRTIMERS turned on
      - Compile using EABI, let's assume recent compilers are used
        now (tested using GCC 4.4.1)
      - Remove forced 32MiB at command line, the bootloader usually
        knows this better, and my U-Boot patches nowadays make that
        boot loader pass the correct adjusted value
      - Enable the MTD Physmap flash driver, so that the changes done
        earlier by Marc Zyngier replacing integrator-flash takes
        effect
      - Enable the PL030 RTC driver that has not been default-compiled
        with any config for a while
      
      This has been tested on the real hardware Integrator AP with
      both an ARM920T and ARM926EJ-S core module.
      
      Cc: Marc Zyngier <Marc.Zyngier@arm.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      a675002c
  20. 14 10月, 2011 1 次提交
    • O
      ARM: tegra: update defconfig · ecb7b0e3
      Olof Johansson 提交于
      Refresh tegra_defconfig:
      
      New options enabled: RTC, SPI, USB and USB_STORAGE together with
      corresponding tegra drivers. Also enable some of the common usb ethernet
      adapters.
      
      Enable Tegra ALSA/ASoC/sound support, including drivers for TrimSlice,
      and WM8903-based platforms such as Harmony and Seaboard.
      
      Finally, enable new merged boards (Ventana) and the generic devicetree board.
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      Acked-by: NStephen Warren <swarren@nvidia.com>
      ecb7b0e3
  21. 13 10月, 2011 1 次提交
  22. 09 10月, 2011 1 次提交
  23. 07 10月, 2011 1 次提交
  24. 25 8月, 2011 2 次提交
  25. 21 7月, 2011 2 次提交
  26. 18 7月, 2011 1 次提交
    • N
      ARM: mach-loki: delete · c8b7d43b
      Nicolas Pitre 提交于
      This was introduced more than 3 years ago, and since then only generic
      janitorial changes were made without further addition of actual support
      for "real" devices.  This is therefore a cost with no benefits to keep
      in the tree.  If someone wishes to revive this code, it is always
      possible to retrieve it from the Git repository.
      Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
      CC: Ke Wei <kewei@marvell.com>
      CC: Saeed Bishara <saeed@marvell.com>
      CC: Lennert Buytenhek <buytenh@wantstofly.org>
      c8b7d43b
  27. 11 7月, 2011 1 次提交
  28. 07 7月, 2011 3 次提交
  29. 23 6月, 2011 1 次提交
  30. 21 6月, 2011 1 次提交