sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl
register bit no. 23:25, with following possibilities

   0XX: pll1_clk
   10X: sys_synth_clk
   110: pll2_clk
   111: pll3_clk

Out of several possibilities (h/w wise) to select same clock parent for
sys_clk, current clock implementation was considering just one value.

When bootloader programmed different (valid) value to select a clock
parent then Linux breaks.

Here, we try to include all possibilities which can lead to same
clock selection thus making Linux independent of bootloader selection
values.
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

This patch is to fix typing mistake of clk enable register of i2c1 and
uart1.
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

The max limit of con_id is 16 and dev_id is 20. As of now for spear6xx, many clk
ids are exceeding this predefined limit.

This patch is intended to rename clk ids like:
    mux_clk -> _mclk
    gate_clk -> _gclk
    synth_clk -> syn_clk
    ras_gen1_synth_gate_clk -> ras_syn1_gclk
    pll3_48m -> pll3_
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

The max limit of con_id is 16 and dev_id is 20. As of now for spear3xx, many clk
ids are exceeding this predefined limit.

This patch is intended to rename clk ids like:
    mux_clk -> _mclk
    gate_clk -> _gclk
    synth_clk -> syn_clk
    ras_gen1_synth_gate_clk -> ras_syn1_gclk
    ras_pll3_48m -> ras_pll3_
    pll3_48m -> pll3_
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

The max limit of con_id is 16 and dev_id is 20. As of now for spear1310, many
clk ids are exceeding this predefined limit.

This patch is intended to rename clk ids like:
    mux_clk -> _mclk
    gate_clk -> _gclk
    synth_clk -> syn_clk
    gmac_phy -> phy_
    gmii_125m_pad -> gmii_pad
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

The max limit of con_id is 16 and dev_id is 20. As of now for spear1340, many
clk ids are exceeding this predefined limit.

This patch rename clk ids like:
    mux_clk -> _mclk
    gate_clk -> _gclk
    synth_clk -> syn_clk
    gmac_phy -> phy_
    gmii_125m_pad_ -> gmii_pad
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

The below commit introduced a bug in __clk_set_parent()
which could cause it to *skip* the parent validation
which makes sure the parent passed to the api is a valid
one.

    commit 7975059d
    Author: Rajendra Nayak <rnayak@ti.com>
    Date:   Wed Jun 6 14:41:31 2012 +0530

        clk: Allow late cache allocation for clk->parents

This was identified by the following compiler warning..

    drivers/clk/clk.c: In function '__clk_set_parent':
    drivers/clk/clk.c:1083:5: warning: 'i' may be used uninitialized in this function [-Wuninitialized]

.. as reported by Marc Kleine-Budde.

There were various options discussed on how to fix this, one
being initing 'i' to clk->num_parents, but the below approach
was found to be more appropriate as it also makes the 'parent
validation' code simpler to read.
Reported-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Cc: stable@kernel.org

The struct clk_lookup are marked as __initdata, resulting in being
removed from memory after the kernel finished booting. However this
leads to a NULL pointer de-ref if loading a module which uses clk_get.

This patch removes the __initdata from the struct clk_lookup.
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The definition of clocks ref_io0 and ref_io1 were inverted.  It causes
a mmc regression on some boards right away.  Fix the regression by
correcting the ref_io clock definition.
Reported-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

clk_change_rate() is accessing parent's rate without checking
if the parent exists at all. In case of root clocks this will
cause NULL pointer dereference.

This patch follows what clk_calc_new_rates() does in such
situation.
Signed-off-by: NPawel Moll <pawel.moll@arm.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Cc: stable@kernel.org

Parent clocks for muxes are cached in clk->parents to
avoid frequent lookups, however the cache allocation happens
only during clock registeration and later clk_set_parent()
assumes a cache space available and allocated.

This is not entirely true for platforms which do early clock
registerations wherein the cache allocation using kzalloc
could fail during clock registeration.

Allow cache allocation to happen later as part of clk_set_parent()
to help such cases and avoid crashes assuming a cache being
available.

While here also replace existing kmalloc() with kzalloc()
in the file.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Cc: stable@kernel.org

Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@st.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

viresh.kumar@st.com email-id doesn't exist anymore as I have left the
company.  Replace ST's id with viresh.linux@gmail.com.

It also updates .mailmap file to fix address for 'git shortlog'
Signed-off-by: NViresh Kumar <viresh.linux@gmail.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The clk_set_rate() code shouldn't check the clock's enable count when
validating CLK_SET_RATE_GATE flag since the enable count could change after
the validation. Similar to clk_set_parent(), it should instead check the
prepare count. The prepare count should go to zero only when the end user
expects the clock to not be enabled in the future. Since the code already
grabs the prepare count before validation, it's not possible for prepare
count to change after validation and by association not possible for a well
behaving end user to enable the clock while the set rate is in progress.
Signed-off-by: NSaravana Kannan <skannan@codeaurora.org>
Reviewed-by: NRichard Zhao <richard.zhao@freescale.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

While there's no actual implementation behind it having the call to use
in drivers makes them feel neater from a driver author point of view. An
actual implementation can wait for someone who needs to use the function
in a real system.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
[mturquette@linaro.org: void return type instead of int -EINVAL]
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds SPEAr1310 and SPEAr1340's clock framework support. It is based
on earlier support for SPEAr3xx family.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@ti.com>

The register HW_SSP_VERSION is broken for ssp version detection,
as the address of the register is different between imx23 and imx28.
Let's use platform_device_id to detect the device, so that the use
of cpu_is_xxx can be removed.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NChris Ball <cjb@laptop.org>

SPEAr SoCs used its own clock framework since now. From now on they will move to
use common clock framework.

This patch updates existing SPEAr machine support to adapt for common clock
framework.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

All SPEAr SoC's contain GPT Synthesizers. Their Fout is derived from
following equations:

Fout= Fin/((2 ^ (N+1)) * (M+1))

This patch adds in support for this type of clock.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>

All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from
following equations:

Fout = Fin / (2 * div) (division factor)
div is 17 bits:-
     0-13 (fractional part)
     14-16 (integer part)
     div is (16-14 bits).(13-0 bits) (in binary)

     Fout = Fin/(2 * div)
     Fout = ((Fin / 10000)/(2 * div)) * 10000
     Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
     Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000

div << 14 is simply 17 bit value written at register.

This patch adds in support for this type of clock.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>

All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on
values of eq, x and y.

Fout from synthesizer can be given from two equations:
Fout1 = (Fin * X/Y)/2		EQ1
Fout2 = Fin * X/Y		EQ2

This patch adds in support for this type of clock.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>

All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations

- In normal mode
  vco = (2 * M[15:8] * Fin)/N

- In Dithered mode
  vco = (2 * M[15:0] * Fin)/(256 * N)

pll_rate = vco/2^p

vco and pll are very closely bound to each other,
"vco needs to program: mode, m & n" and "pll needs to program p",
both share common enable/disable logic and registers.

This patch adds in support for this type of clock.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>

Rewrite mxs_dma_is_apbh and mxs_dma_is_apbx in order to support
other SoCs like imx6q and reform the platform_device_id for the
better further dt support.

Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Huang Shijie <b32955@freescale.com>
Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NMarek Vasut <marex@denx.de>
Acked-by: NVinod Koul <vinod.koul@intel.com>

It adds initial device tree support for imx23-evk board, and only
serial console is enabled.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NMarek Vasut <marex@denx.de>

This patch includes basic dt support which can boot via nfs rootfs.
Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NMarek Vasut <marex@denx.de>

Having fixed factors/dividers in hardware is a common pattern, so
add a basic clock type doing this. It basically describes a fixed
factor clock using a nominator and a denominator.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NViresh Kumar <viresh.kumar@st.com>
Tested-by: NShawn Guo <shawn.guo@linaro.org>
[mturquette@linaro.org: constify parent_names in static init macro]
[mturquette@linaro.org: copy/paste bug from mux in static init macro]
[mturquette@linaro.org: fix error handling in clk_register_fixed_factor]
[mturquette@linaro.org: improve division accuracy; thanks to Saravana]
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The original conversion to struct clk_hw_init failed to add the pointer
assignment in clk_register_mux.
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Reported-by: NSascha Hauer <s.hauer@pengutronix.de>

Exposing this option generates confusion and incorrect behavior for
single-image builds across platforms.  Enable this behavior permanently.
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NSaravana Kannan <skannan@codeaurora.org>

Patch 'clk: always pass parent_rate into .round_rate' made a subtle
change to the semantics of .round_rate.  It is now expected for the
parent's rate to always be passed in, simplifying the implemenation of
various .round_rate callback definitions.

However the patch also introduced a bug in clk_calc_new_rates whereby a
clock without the CLK_SET_RATE_PARENT flag set could still propagate a
rate change up to a parent clock if the the .round_rate callback
modified the &best_parent_rate value in any way.

This patch fixes the issue at the framework level (in
clk_calc_new_rates) by specifically handling the case where the
CLK_SET_RATE_PARENT flag is not set.
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>

With old mxs clock support removed, the timer_clk argument of
mxs_timer_init is unused now, so remove it.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

It switches mxs clock support to common clk framework based drivers.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add imx28 clock support based on common clk framework.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add imx23 clock support based on common clk framework.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add mxs specific clocks, pll, reference clock (PFD), integer divider
and fractional divider.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The common clock framework allocates clocks dynamically.  Provide a
set of helpers to streamline the clkdev registration of the clock
lookups to avoid repetitive code sequences.
Reviewed-by: NViresh Kumar <viresh.kumar@st.com>
Tested-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This is well documented but isn't implemented. clk_set_rate() must check if
flags have CLK_SET_RATE_GATE bit set and is enabled too.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Create a struct clk_init_data to hold all data that needs to be passed from
the platfrom specific driver to the common clock framework during clock
registration. Add a pointer to this struct inside clk_hw.

This has several advantages:
* Completely hides struct clk from many clock platform drivers and static
  clock initialization code that don't care for static initialization of
  the struct clks.
* For platforms that want to do complete static initialization, it removed
  the need to directly mess with the struct clk's fields while still
  allowing to statically allocate struct clk. This keeps the code more
  future proof even if they include clk-private.h.
* Simplifies the generic clk_register() function and allows adding optional
  fields in the future without modifying the function signature.
* Simplifies the static initialization of clocks on all platforms by
  removing the need for forward delcarations or convoluted macros.
Signed-off-by: NSaravana Kannan <skannan@codeaurora.org>
[mturquette@linaro.org: kept DEFINE_CLK_* macros and __clk_init]
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergman <arnd.bergmann@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Jamie Iles <jamie@jamieiles.com>
Cc: Richard Zhao <richard.zhao@linaro.org>
Cc: Saravana Kannan <skannan@codeaurora.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Deepak Saxena <dsaxena@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>

Using the common clock infrastructure without the common clkdev code makes
little sense, so select CLKDEV_LOOKUP for COMMON_CLK.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) is true, then
we don't need to set clk->new_rate here, as we will call clk_calc_subtree()
afterwards and it also sets clk->new_rate.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch tries to remove duplicate code for clk_gate clocks. This creates
another routine clk_gate_endisable() which will take care of enable/disable
clock with knowledge of CLK_GATE_SET_TO_DISABLE flag.

It works on following logic:

For enabling clock, enable = 1
	set2dis = 1	-> clear bit	-> set = 0
	set2dis = 0	-> set bit	-> set = 1

For disabling clock, enable = 0
	set2dis = 1	-> set bit	-> set = 1
	set2dis = 0	-> clear bit	-> set = 0

So, result is always: enable xor set2dis.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>