1. 21 3月, 2006 17 次提交
  2. 20 3月, 2006 23 次提交
    • D
      [SPARC64]: Fix 2 bugs in huge page support. · f6b83f07
      David S. Miller 提交于
      1) huge_pte_offset() did not check the page table hierarchy
         elements as being empty correctly, resulting in an OOPS
      
      2) Need platform specific hugetlb_get_unmapped_area() to handle
         the top-down vs. bottom-up address space allocation strategies.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      f6b83f07
    • D
      [SPARC64]: Optimized TSB table initialization. · bb8646d8
      David S. Miller 提交于
      We only need to write an invalid tag every 16 bytes,
      so taking advantage of this can save many instructions
      compared to the simple memset() call we make now.
      
      A prefetching implementation is implemented for sun4u
      and a block-init store version if implemented for Niagara.
      
      The next trick is to be able to perform an init and
      a copy_tsb() in parallel when growing a TSB table.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      bb8646d8
    • D
      [SPARC64]: Increase top of 32-bit process stack. · d61e16df
      David S. Miller 提交于
      Put it one page below the top of the 32-bit address space.
      This gives us ~16MB more address space to work with.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d61e16df
    • D
      [SPARC64]: Top-down address space allocation for 32-bit tasks. · a91690dd
      David S. Miller 提交于
      Currently allocations are very constrained for 32-bit processes.
      It grows down-up from 0x70000000 to 0xf0000000 which gives about
      2GB of stack + dynamic mmap() space.
      
      So support the top-down method, and we need to override the
      generic helper function in order to deal with D-cache coloring.
      
      With these changes I was able to squeeze out a mmap() just over
      3.6GB in size in a 32-bit process.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a91690dd
    • D
      [SPARC64]: Fix and re-enable dynamic TSB sizing. · 7a1ac526
      David S. Miller 提交于
      This is good for up to %50 performance improvement of some test cases.
      The problem has been the race conditions, and hopefully I've plugged
      them all up here.
      
      1) There was a serious race in switch_mm() wrt. lazy TLB
         switching to and from kernel threads.
      
         We could erroneously skip a tsb_context_switch() and thus
         use a stale TSB across a TSB grow event.
      
         There is a big comment now in that function describing
         exactly how it can happen.
      
      2) All code paths that do something with the TSB need to be
         guarded with the mm->context.lock spinlock.  This makes
         page table flushing paths properly synchronize with both
         TSB growing and TLB context changes.
      
      3) TSB growing events are moved to the end of successful fault
         processing.  Previously it was in update_mmu_cache() but
         that is deadlock prone.  At the end of do_sparc64_fault()
         we hold no spinlocks that could deadlock the TSB grow
         sequence.  We also have dropped the address space semaphore.
      
      While we're here, add prefetching to the copy_tsb() routine
      and put it in assembler into the tsb.S file.  This piece of
      code is quite time critical.
      
      There are some small negative side effects to this code which
      can be improved upon.  In particular we grab the mm->context.lock
      even for the tsb insert done by update_mmu_cache() now and that's
      a bit excessive.  We can get rid of that locking, and the same
      lock taking in flush_tsb_user(), by disabling PSTATE_IE around
      the whole operation including the capturing of the tsb pointer
      and tsb_nentries value.  That would work because anyone growing
      the TSB won't free up the old TSB until all cpus respond to the
      TSB change cross call.
      
      I'm not quite so confident in that optimization to put it in
      right now, but eventually we might be able to and the description
      is here for reference.
      
      This code seems very solid now.  It passes several parallel GCC
      bootstrap builds, and our favorite "nut cruncher" stress test which is
      a full "make -j8192" build of a "make allmodconfig" kernel.  That puts
      about 256 processes on each cpu's run queue, makes lots of process cpu
      migrations occur, causes lots of page table and TLB flushing activity,
      incurs many context version number changes, and it swaps the machine
      real far out to disk even though there is 16GB of ram on this test
      system. :-)
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      7a1ac526
    • D
      [SPARC64]: Fix system type in /proc/cpuinfo and remove bogus OBP check. · 90a6646b
      David S. Miller 提交于
      Report 'sun4v' when appropriate in /proc/cpuinfo
      
      Remove all the verifications of the OBP version string.  Just
      make sure it's there, and report it raw in the bootup logs and
      via /proc/cpuinfo.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      90a6646b
    • D
      [SPARC64]: Add SMT scheduling support for Niagara. · 8935dced
      David S. Miller 提交于
      The mapping is a simple "(cpuid >> 2) == core" for now.
      Later we'll add more sophisticated code that will walk
      the sun4v machine description and figure this out from
      there.
      
      We should also add core mappings for jaguar and panther
      processors.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8935dced
    • D
      [SPARC64]: Move over to sparsemem. · d1112018
      David S. Miller 提交于
      This has been pending for a long time, and the fact
      that we waste a ton of ram on some configurations
      kind of pushed things over the edge.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d1112018
    • D
      [SPARC64]: Fix new context version SMP handling. · ee29074d
      David S. Miller 提交于
      Don't piggy back the SMP receive signal code to do the
      context version change handling.
      
      Instead allocate another fixed PIL number for this
      asynchronous cross-call.  We can't use smp_call_function()
      because this thing is invoked with interrupts disabled
      and a few spinlocks held.
      
      Also, fix smp_call_function_mask() to count "cpus" correctly.
      There is no guarentee that the local cpu is in the mask
      yet that is exactly what this code was assuming.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ee29074d
    • D
      [SPARC64]: Bulletproof MMU context locking. · a77754b4
      David S. Miller 提交于
      1) Always spin_lock_init() in init_context().  The caller essentially
         clears it out, or copies the mm info from the parent.  In both
         cases we need to explicitly initialize the spinlock.
      
      2) Always do explicit IRQ disabling while taking mm->context.lock
         and ctx_alloc_lock.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a77754b4
    • D
      [SPARC64]: Do not allow mapping pages within 4GB of 64-bit VA hole. · 8bcd1741
      David S. Miller 提交于
      The UltraSPARC T1 manual recommends this because the chip
      could instruction prefetch into the VA hole, and this would
      also make decoding  certain kinds of memory access traps
      more difficult (because the chip sign extends certain pieces
      of trap state).
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8bcd1741
    • D
      [SPARC64]: Kill bogus function externs in asm/pgtable.h · e2299045
      David S. Miller 提交于
      These are all implemented inline earlier in the file.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e2299045
    • D
      [SPARC64]: Fix bugs in SUN4V cpu mondo dispatch. · b830ab66
      David S. Miller 提交于
      There were several bugs in the SUN4V cpu mondo dispatch code.
      
      In fact, if we ever got a EWOULDBLOCK or other error from
      the hypervisor call, we'd potentially send a cpu mondo multiple
      times to the same cpu and even worse we could loop until the
      timeout resending the same mondo over and over to such cpus.
      
      So let's bulletproof this thing as follows:
      
      1) Implement cpu_mondo_send() and cpu_state() hypervisor calls
         in arch/sparc64/kernel/entry.S, add prototypes to asm/hypervisor.h
      
      2) Don't build and update the cpulist using inline functions, this
         was causing the cpu mask to not get updated in the caller.
      
      3) Disable interrupts during the entire mondo send, otherwise our
         cpu list and/or mondo block could get overwritten if we take
         an interrupt and do a cpu mondo send on the current cpu.
      
      4) Check for all possible error return types from the cpu_mondo_send()
         hypervisor call.  In particular:
      
         HV_EOK) Our work is done, all cpus have received the mondo.
         HV_CPUERROR) One or more of the cpus in the cpu list we passed
                      to the hypervisor are in error state.  Use cpu_state()
                      calls over the entries in the cpu list to see which
      		ones.  Record them in "error_mask" and report this
      		after we are done sending the mondo to cpus which are
      		not in error state.
         HV_EWOULDBLOCK) We need to keep trying.
      
         Any other error we consider fatal, we report the event and exit
         immediately.
      
      5) We only timeout if forward progress is not made.  Forward progress
         is defined as having at least one cpu get the mondo successfully
         in a given cpu_mondo_send() call.  Otherwise we bump a counter
         and delay a little.  If the counter hits a limit, we signal an
         error and report the event.
      
      Also, smp_call_function_mask() error handling reports the number
      of cpus incorrectly.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b830ab66
    • D
      [SPARC64]: Use 13-bit context size always. · 97c4b6f9
      David S. Miller 提交于
      We no longer have the problems that require using the smaller
      sizes.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      97c4b6f9
    • D
      36344762
    • D
      [SPARC64]: Fix TLB context allocation with SMT style shared TLBs. · a0663a79
      David S. Miller 提交于
      The context allocation scheme we use depends upon there being a 1<-->1
      mapping from cpu to physical TLB for correctness.  Chips like Niagara
      break this assumption.
      
      So what we do is notify all cpus with a cross call when the context
      version number changes, and if necessary this makes them allocate
      a valid context for the address space they are running at the time.
      
      Stress tested with make -j1024, make -j2048, and make -j4096 kernel
      builds on a 32-strand, 8 core, T2000 with 16GB of ram.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a0663a79
    • D
      [SPARC64]: Fix %tstate ASI handling in start_thread{,32}() · 0f05da6d
      David S. Miller 提交于
      Niagara helps us find a ancient bug in the sparc64 port :-)
      
      The ASI_* values are plain constant defines, thus signed 32-bit
      on sparc64.  To put shift this into the regs->tstate value we were
      doing or'ing "(ASI_PNF << 24)" into there.
      
      ASI_PNF is 0x82 and shifted left by 24 makes that topmost bit the
      sign bit in a 32-bit value.  This would get sign extended to 64-bits
      and thus corrupt the top-half of the reg->tstate value.
      
      This never caused problems in pre-Niagara cpus because the only thing
      up there were the condition code values.  But Niagara has the global
      register level field, and this all 1's value is illegal there so
      Niagara gives an illegal instruction trap due to this bug.
      
      I'm pretty sure this bug is about as old as the sparc64 port itself.
      
      This also points out that we weren't setting ASI_PNF for 32-bit tasks.
      We should, so fix that while we're here.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0f05da6d
    • D
      [SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings. · d7744a09
      David S. Miller 提交于
      It can map all of the linear kernel mappings with zero TSB hash
      conflicts for systems with 16GB or less ram.  In such cases, on
      SUN4V, once we load up this TSB the first time with all the
      mappings, we never take a linear kernel mapping TLB miss ever
      again, the hypervisor handles them all.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d7744a09
    • D
      [SPARC64]: Add sun4v_cpu_yield(). · 6f5374c9
      David S. Miller 提交于
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6f5374c9
    • D
      [SPARC64]: Kill cpudata->idle_volume. · 1bd0cd74
      David S. Miller 提交于
      Set, but never used.
      
      We used to use this for dynamic IRQ retargetting, but that
      code died a long time ago.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1bd0cd74
    • D
      [SPARC64]: Export a PAGE_SHARED symbol. · 0f15952a
      David S. Miller 提交于
      For drivers/media/*, noticed by Fabbione.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0f15952a
    • F
    • D
      [SPARC64]: More TLB/TSB handling fixes. · 8b234274
      David S. Miller 提交于
      The SUN4V convention with non-shared TSBs is that the context
      bit of the TAG is clear.  So we have to choose an "invalid"
      bit and initialize new TSBs appropriately.  Otherwise a zero
      TAG looks "valid".
      
      Make sure, for the window fixup cases, that we use the right
      global registers and that we don't potentially trample on
      the live global registers in etrap/rtrap handling (%g2 and
      %g6) and that we put the missing virtual address properly
      in %g5.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8b234274