- 03 8月, 2012 1 次提交
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由 Barry Song 提交于
The only way to write LATCHED registers to write LATCH_BIT to LATCH register, that will latch COUNTER into LATCHED.e.g. writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); Writing values to LATCHED registers directly is useless at all. Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 03 2月, 2012 1 次提交
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由 Marc Zyngier 提交于
Prima2 has its own sched_clock() implementation, which gets in the way of a single zImage. Moving to the common sched_clock framework makes the code slightly cleaner (the mapping hack in sched_clock() goes away...). Acked-by: NBarry Song <baohua.song@csr.com> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
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- 01 10月, 2011 2 次提交
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由 Barry Song 提交于
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
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由 Barry Song 提交于
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
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- 21 9月, 2011 1 次提交
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由 Barry Song 提交于
SiRFprimaII will lose power in deepsleep mode except rtc, pmu and sdram self-refresh. This patch saves timer-related registers while suspending and restore them while resuming. Signed-off-by: NBarry Song <baohua.song@csr.com> Acked-by: NArnd Bergmann <arnd@arndb.de>
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- 11 9月, 2011 1 次提交
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由 Jamie Iles 提交于
The of_device_id tables used for matching should be terminated with empty sentinel values. Signed-off-by: NJamie Iles <jamie@jamieiles.com> Signed-off-by: NBarry Song <baohua.song@csr.com>
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- 09 7月, 2011 1 次提交
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由 Binghua Duan 提交于
SiRFprimaII is the latest generation application processor from CSR’s Multifunction SoC product family. Designed around an ARM cortex A9 core, high-speed memory bus, advanced 3D accelerator and full-HD multi-format video decoder, SiRFprimaII is able to meet the needs of complicated applications for modern multifunction devices that require heavy concurrent applications and fluid user experience. Integrated with GPS baseband, analog and PMU, this new platform is designed to provide a cost effective solution for Automotive and Consumer markets. This patch adds the basic support for this SoC and EVB board based on device tree. It is following the ZYNQ of Xilinx in some degree. Signed-off-by: NBinghua Duan <Binghua.Duan@csr.com> Signed-off-by: NRongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: NZhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: NYuping Luo <Yuping.Luo@csr.com> Signed-off-by: NBin Shi <Bin.Shi@csr.com> Signed-off-by: NHuayi Li <Huayi.Li@csr.com> Signed-off-by: NBarry Song <Baohua.Song@csr.com> Reviewed-by: NArnd Bergmann <arnd@arndb.de>
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