Make FSL eSPI CSnBEF and CSnAFT fields in ESPI_SPMODEn registers
(n=0,1,2,3) configurable through device tree.

CSnBEF is the chip select setup time.  It's the delay in bits from the
activation of chip select pin to the first clock for data frame.

CSnAFT is the chip select hold time.  It's the delay in bits from the
last clock for data frame to the deactivation of chip select pin.

The FSL eSPI driver hardcodes CSnBEF and CSnAFT to 0.  Need to set
them to a different value for some device.
Signed-off-by: NJane Wan <Jane.Wan@gainspeed.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

This adds support for the mostly register-compatible SPICTRL cores from the
GRLIB VHDL IP core library from Aeroflex Gaisler. They are normally running on
SPARC. A different entry in of_fsl_spi_match matches this core and indicates a
different hardware type that is used to set up different function pointers and
special cases.

The GRLIB core operates in cpu mode. The number of bits per word might be
limited. There might be native chipselects selected via a slave select
register. These differences to the FSL type cores, if present, are indicated by
a capabilities register. Other register and function differences exists but are
not relevant to the driver.
Acked-by: NAnton Vorontsov <anton@enomsg.org>
Signed-off-by: NAndreas Larsson <andreas@gaisler.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This makes the spi-fsl-spi driver usable in CPU mode outside of an FSL_SOC and
even an powerpc environment by moving CPM mode functionality to a separate file
that is only compiled and linked in an FSL_SOC environment and adding some
ifdefs to hide types and functions or provide alternatives.

For devicetree probing a "clock-frequency" property is used for clock frequency
instead of calls to FSL_SOC-specific functions.
Acked-by: NAnton Vorontsov <anton@enomsg.org>
Signed-off-by: NAndreas Larsson <andreas@gaisler.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The device tree is used by more than just PowerPC.  Make the documentation
directory available to all.

v2: reorganized files while moving to create arch and driver specific
    directories.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Also modifiy the document of cell-index in SPI controller. Add the
SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Added devicetree binding documentation for gpios used as chipselect. The
code to evaluate these is already present in spi_mpc8xxx.c.
Signed-off-by: NErnst Schwab <eschwab@online.de>
Reviewed-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Moved Freescale SoC related bindings out of booting-without-of.txt and into
their own files.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>