The devm_[kzalloc|ioremap] functions allocates data that are released
when a driver detaches. Thus, there is no reason to explicitly call
devm_[kfree|iounmap] in probe or remove functions.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NJoerg Roedel <joro@8bytes.org>

When enabling LPAE on ARM, phys_addr_t becomes 64 bits wide and printing
a variable of that type using a simple %x format specifier causes the
compiler to complain. Change the format specifier to %pa, which is used
specifically for variables of type phys_addr_t.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NJoerg Roedel <joro@8bytes.org>

Fix printk formats for dma_addr_t:

   drivers/iommu/tegra-smmu.c: In function 'smmu_iommu_iova_to_phys':
>> drivers/iommu/tegra-smmu.c:774:2: warning: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'dma_addr_t' [-Wformat]
--
   drivers/iommu/tegra-gart.c: In function 'gart_iommu_iova_to_phys':
>> drivers/iommu/tegra-gart.c:298:3: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'dma_addr_t' [-Wformat]
Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: NJoerg Roedel <joro@8bytes.org>

This is required in case of PAMU, as it can support a window size of up
to 64G (even on 32bit).
Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: NJoerg Roedel <joro@8bytes.org>

Tegra only supports, and always enables, device tree. Remove all ifdefs
for DT support from the driver.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NJoerg Roedel <joro@8bytes.org>

CONFIG_HOTPLUG is going away as an option.  As a result, the __dev*
markings need to be removed.

This change removes the use of __devinit, __devexit_p, __devinitdata,
and __devexit from these drivers.

Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.

Cc: Bill Pemberton <wfp5p@virginia.edu>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Omar Ramirez Luna <omar.luna@linaro.org>
Cc: Mauro Carvalho Chehab <mchehab@redhat.com>
Cc: Hiroshi Doyu <hdoyu@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Bharat Nihalani <bnihalani@nvidia.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

For a single image to support multiple SoCs(GART/SMMU).
Reported-by: NArto Merilainen <amerilainen@nvidia.com>
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NJoerg Roedel <joro@8bytes.org>

Implement the attribute for the Tegra IOMMU drivers.
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>

DT passes the exact GART register ranges without any overlapping with
MC register ranges. GART register offset needs to be adjusted by one
passed by DT correctly.
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>

This commit adds device tree support for the GART hardware available on
NVIDIA Tegra 20 SoCs.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>

Pass the correct gart device pointer.
Reviewed-by: NVandana Salve <vsalve@nvidia.com>
Tested-by: NVandana Salve <vsalve@nvidia.com>
Reviewed-by: NHiroshi Doyu <hdoyu@nvidia.com>
Reviewed-by: NBharat Nihalani <bnihalani@nvidia.com>
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>

This must have been messed up while merging, the intention was
clearly to unlock there.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>

Tegra 20 IOMMU H/W, GART (Graphics Address Relocation Table). This
patch implements struct iommu_ops for GART for the upper IOMMU API.

This H/W module supports only single virtual address space(domain),
and manages a single level 1-to-1 mapping H/W translation page table.

[With small fixes by Joerg Roedel]
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>