1. 13 4月, 2014 1 次提交
  2. 10 3月, 2014 1 次提交
    • A
      iwlwifi: pcie: enable LP XTAL to reduce power consumption · a812cba9
      Alexander Bondar 提交于
      1. Enable LP XTAL to avoid HW bug where device may consume much
      power if FW is not loaded after device reset. LP XTAL is
      disabled by default after device HW reset. Configure device's
      "persistence" mode to avoid resetting XTAL again when SHRD_HW_RST
      occurs in S3.
      
      2. Add methods to access SHR (shared block memory space) directly from PCI
      bus w/o need to power up MAC HW.
      
      Shared internal registers (e.g. SHR_APMG_GP1, SHR_APMG_XTAL_CFG)can be
      accessed directly from PCI bus through SHR arbiter even when MAC HW is
      powered down. This is possible due to indirect read/write via
      HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and HEEP_CTRL_WRD_PCIEX_DATA (0xF4)
      registers.
      
      Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
      need not be powered up so no "grab inc access" is required.
      
      For example, to read from SHR_APMG_GP1 register (0x1DC),
      first, write to the control register:
      HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
      HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
      second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
      
      To write the register, first, write to the data register
      HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
      HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
      HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
      Signed-off-by: NAlexander Bondar <alexander.bondar@intel.com>
      Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
      a812cba9
  3. 04 2月, 2014 2 次提交
  4. 14 1月, 2014 1 次提交
  5. 01 1月, 2014 1 次提交
  6. 10 12月, 2013 1 次提交
  7. 03 10月, 2013 1 次提交
  8. 06 8月, 2013 1 次提交
  9. 26 7月, 2013 1 次提交
  10. 29 5月, 2013 1 次提交
  11. 06 3月, 2013 1 次提交
  12. 31 1月, 2013 1 次提交
  13. 24 1月, 2013 1 次提交
  14. 16 10月, 2012 1 次提交
  15. 09 6月, 2012 1 次提交
  16. 06 6月, 2012 1 次提交
  17. 25 4月, 2012 1 次提交
    • J
      iwlwifi: fix hardware queue programming · 5ef4acd5
      Johannes Berg 提交于
      Newer devices have 20 (5000 series) or 30 (6000 series)
      hardware queues, rather than the 16 that 4965 had. This
      was added to the driver a long time ago, but improperly:
      the queue registers for the higher queues aren't just
      continuations of the registers for the first 16 queues,
      they are in other places. Therefore, the hardware would
      lock up when trying to activate queue 16 or above and
      the device would have to be restarted.
      
      Thanks goes to Emmanuel who identified this and told me
      how the queue programming should be done.
      
      Note that we don't use queues 20 and higher today and
      doing so needs more work than this.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
      Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com>
      Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
      5ef4acd5
  18. 10 3月, 2012 1 次提交
  19. 25 1月, 2012 1 次提交
  20. 07 1月, 2012 1 次提交
  21. 30 8月, 2011 2 次提交
  22. 16 7月, 2011 1 次提交
  23. 01 7月, 2011 1 次提交
  24. 08 4月, 2011 4 次提交
  25. 14 12月, 2010 1 次提交
  26. 27 8月, 2010 1 次提交
  27. 17 4月, 2010 1 次提交
  28. 10 3月, 2010 1 次提交
    • J
      iwlwifi: clean up queue/fifo handling · edc1a3a0
      Johannes Berg 提交于
      4965 hardware has 7 queues reserved and the
      remaining ones used for aggregation, 5000
      and higher need to have 10 reserved. This
      is not very clear in the code right now,
      unfortunately.
      
      Introduce a new IWL_TX_FIFO_UNUSED constant
      and make the queue/FIFO mapping arrays able
      to hold that value, and change the setup
      code to reserve all queues in the arrays
      (the queue number is the index) and use the
      new unused constant to not map those queues
      to any FIFO.
      
      Additionally, clear up the AC/queue mapping
      code to be more understandable. The mapping
      is the identity mapping right now, but with
      the mapping function I think it's easier to
      understand what happens there.
      
      Finally, HCCA isn't implemented at all and
      I think newer microcode removed it, so let's
      remove all mention of it in the code, some
      comments remain for 4965.
      Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
      Acked-by: NShanyu Zhao <shanyu.zhao@intel.com>
      Signed-off-by: NReinette Chatre <reinette.chatre@intel.com>
      edc1a3a0
  29. 20 1月, 2010 1 次提交
  30. 12 11月, 2009 1 次提交
  31. 25 7月, 2009 1 次提交
  32. 30 1月, 2009 1 次提交
  33. 13 12月, 2008 1 次提交
  34. 01 11月, 2008 1 次提交
  35. 05 8月, 2008 1 次提交