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  1. 08 6月, 2012 1 次提交
  3. 21 9月, 2011 1 次提交
  5. 13 9月, 2011 2 次提交
  7. 05 10月, 2009 1 次提交
  9. 11 9月, 2009 1 次提交
    • Y
      intel-iommu: Fix kernel hang if interrupt remapping disabled in BIOS · 074835f0
      由 Youquan Song 提交于 
      BIOS clear DMAR table INTR_REMAP flag to disable interrupt remapping. Current
kernel only check interrupt remapping(IR) flag in DRHD's extended capability
register to decide interrupt remapping support or not. But IR flag will not
change when BIOS disable/enable interrupt remapping.

When user disable interrupt remapping in BIOS or BIOS often defaultly disable
interrupt remapping feature when BIOS is not mature.Though BIOS disable
interrupt remapping but intr_remapping_supported function will always report
to OS support interrupt remapping if VT-d2 chipset populated. On this
cases, kernel will continue enable interrupt remapping and result kernel panic.
This bug exist on almost all platforms with interrupt remapping support.

This patch add DMAR table INTR_REMAP flag check before enable interrupt
remapping.
Signed-off-by: NYouquan Song <youquan.song@intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      074835f0
  11. 18 5月, 2009 3 次提交
  13. 11 5月, 2009 2 次提交
    • D
      intel-iommu: Clean up handling of "caching mode" vs. IOTLB flushing. · 1f0ef2aa
      由 David Woodhouse 提交于 
      As we just did for context cache flushing, clean up the logic around
whether we need to flush the iotlb or just the write-buffer, depending
on caching mode.

Fix the same bug in qi_flush_iotlb() that qi_flush_context() had -- it
isn't supposed to be returning an error; it's supposed to be returning a
flag which triggers a write-buffer flush.

Remove some superfluous conditional write-buffer flushes which could
never have happened because they weren't for non-present-to-present
mapping changes anyway.
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      1f0ef2aa
    • D
      intel-iommu: Clean up handling of "caching mode" vs. context flushing. · 4c25a2c1
      由 David Woodhouse 提交于 
      It really doesn't make a lot of sense to have some of the logic to
handle caching vs. non-caching mode duplicated in qi_flush_context() and
__iommu_flush_context(), while the return value indicates whether the
caller should take other action which depends on the same thing.

Especially since qi_flush_context() thought it was returning something
entirely different anyway.

This patch makes qi_flush_context() and __iommu_flush_context() both
return void, removes the 'non_present_entry_flush' argument and makes
the only call site which _set_ that argument to 1 do the right thing.
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      4c25a2c1
  15. 29 4月, 2009 1 次提交
    • F
      Intel IOMMU Pass Through Support · 4ed0d3e6
      由 Fenghua Yu 提交于 
      The patch adds kernel parameter intel_iommu=pt to set up pass through
mode in context mapping entry. This disables DMAR in linux kernel; but
KVM still runs on VT-d and interrupt remapping still works.

In this mode, kernel uses swiotlb for DMA API functions but other VT-d
functionalities are enabled for KVM. KVM always uses multi level
translation page table in VT-d. By default, pass though mode is disabled
in kernel.

This is useful when people don't want to enable VT-d DMAR in kernel but
still want to use KVM and interrupt remapping for reasons like DMAR
performance concern or debug purpose.
Signed-off-by: NFenghua Yu <fenghua.yu@intel.com>
Acked-by: NWeidong Han <weidong@intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      4ed0d3e6
  17. 04 4月, 2009 2 次提交
  19. 24 3月, 2009 1 次提交
  21. 18 3月, 2009 2 次提交
  23. 09 2月, 2009 1 次提交
  25. 29 1月, 2009 1 次提交
  27. 06 1月, 2009 1 次提交
  29. 03 1月, 2009 8 次提交
  31. 18 10月, 2008 1 次提交
  33. 17 10月, 2008 2 次提交
  35. 15 10月, 2008 1 次提交
  37. 12 7月, 2008 8 次提交