1. 24 6月, 2006 16 次提交
  2. 23 6月, 2006 1 次提交
  3. 20 6月, 2006 7 次提交
    • D
      [SPARC64]: Update defconfig. · 4c5eb38a
      David S. Miller 提交于
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4c5eb38a
    • D
      [SPARC64]: Don't double-export synchronize_irq. · c8bfcd95
      David S. Miller 提交于
      It is done by the generic IRQ layer now.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c8bfcd95
    • D
      [SPARC64]: Move over to GENERIC_HARDIRQS. · e18e2a00
      David S. Miller 提交于
      This is the long overdue conversion of sparc64 over to
      the generic IRQ layer.
      
      The kernel image is slightly larger, but the BSS is ~60K
      smaller due to the reduced size of struct ino_bucket.
      
      A lot of IRQ implementation details, including ino_bucket,
      were moved out of asm-sparc64/irq.h and are now private to
      arch/sparc64/kernel/irq.c, and most of the code in irq.c
      totally disappeared.
      
      One thing that's different at the moment is IRQ distribution,
      we do it at enable_irq() time.  If the cpu mask is ALL then
      we round-robin using a global rotating cpu counter, else
      we pick the first cpu in the mask to support single cpu
      targetting.  This is similar to what powerpc's XICS IRQ
      support code does.
      
      This works fine on my UP SB1000, and the SMP build goes
      fine and runs on that machine, but lots of testing on
      different setups is needed.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e18e2a00
    • D
      [SPARC64]: Virtualize IRQ numbers. · 8047e247
      David S. Miller 提交于
      Inspired by PowerPC XICS interrupt support code.
      
      All IRQs are virtualized in order to keep NR_IRQS from needing
      to be too large.  Interrupts on sparc64 are arbitrary 11-bit
      values, but we don't need to define NR_IRQS to 2048 if we
      virtualize the IRQs.
      
      As PCI and SBUS controller drivers build device IRQs, we divy
      out virtual IRQ numbers incrementally starting at 1.  Zero is
      a special virtual IRQ used for the timer interrupt.
      
      So device drivers all see virtual IRQs, and all the normal
      interfaces such as request_irq(), enable_irq(), etc. translate
      that into a real IRQ number in order to configure the IRQ.
      
      At this point knowledge of the struct ino_bucket is almost
      entirely contained within arch/sparc64/kernel/irq.c  There are
      a few small bits in the PCI controller drivers that need to
      be swept away before we can remove ino_bucket's definition
      out of asm-sparc64/irq.h and privately into kernel/irq.c
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8047e247
    • D
      [SPARC64]: Kill ino_bucket->pil · 37cdcd9e
      David S. Miller 提交于
      And reuse that struct member for virt_irq, which will
      be used in future changesets for the implementation of
      mapping between real and virtual IRQ numbers.
      
      This nicely kills off a ton of SBUS and PCI controller
      PIL assignment code which is no longer necessary.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      37cdcd9e
    • D
      [SPARC64]: bp->pil can never be zero · 6a76267f
      David S. Miller 提交于
      Only pil0_dummy_bucket had a pil of zero and we just killed that
      off, so we can delete all special case code that used bp->pil==0
      as a way to identify a dummy bucket.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6a76267f
    • D
      [SPARC64]: Send all device interrupts via one PIL. · fd0504c3
      David S. Miller 提交于
      This is the first in a series of cleanups that will hopefully
      allow a seamless attempt at using the generic IRQ handling
      infrastructure in the Linux kernel.
      
      Define PIL_DEVICE_IRQ and vector all device interrupts through
      there.
      
      Get rid of the ugly pil0_dummy_{bucket,desc}, instead vector
      the timer interrupt directly to a specific handler since the
      timer interrupt is the only event that will be signaled on
      PIL 14.
      
      The irq_worklist is now in the per-cpu trap_block[].
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fd0504c3
  4. 12 6月, 2006 1 次提交
  5. 11 6月, 2006 1 次提交
  6. 10 6月, 2006 2 次提交
  7. 05 6月, 2006 1 次提交
    • D
      [SPARC64]: Fix missing fold at end of checksums. · ae5de0ff
      David S. Miller 提交于
      Both csum_partial() and the csum_partial_copy*() family of routines
      forget to do a final fold on the computed checksum value on sparc64.
      So do the standard Sparc "add + set condition codes, add carry"
      sequence, then make sure the high 32-bits of the return value are
      clear.
      
      Based upon some excellent detective work and debugging done by
      Richard Braun and Samuel Thibault.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ae5de0ff
  8. 31 5月, 2006 1 次提交
  9. 23 5月, 2006 1 次提交
    • D
      [SPARC64]: Respect gfp_t argument to dma_alloc_coherent(). · 42f14237
      David S. Miller 提交于
      Using asm-generic/dma-mapping.h does not work because pushing
      the call down to pci_alloc_coherent() causes the gfp_t argument
      of dma_alloc_coherent() to be ignored.
      
      Fix this by implementing things directly, and adding a gfp_t
      argument we can use in the internal call down to the PCI DMA
      implementation of pci_alloc_coherent().
      
      This fixes massive memory corruption when using the sound driver
      layer, which passes things like __GFP_COMP down into these
      routines and (correctly) expects that to work.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      42f14237
  10. 22 5月, 2006 1 次提交
  11. 13 5月, 2006 1 次提交
  12. 09 5月, 2006 1 次提交
  13. 04 5月, 2006 1 次提交
  14. 01 5月, 2006 2 次提交
  15. 20 4月, 2006 1 次提交
  16. 19 4月, 2006 1 次提交
  17. 18 4月, 2006 1 次提交