* pci/misc:
  PCI: Update documentation 00-INDEX file
  PCI: Convert ioapic to be builtin only, not modular

* pci/host-mvebu:
  PCI: mvebu: Use max_t() instead of max(resource_size_t,)
  PCI: mvebu: Call pci_ioremap_io() at startup instead of dynamically

* pci/host-designware:
  PCI: designware: Fix indent code style

The PCI-DMA-mapping.txt moved to general docs and became DMA-API-HOWTO.txt
in 5e07c2c7 ("Documentation: rename PCI/PCI-DMA-mapping.txt to
DMA-API-HOWTO.txt").  Add new file about PCI Express I/O Virtualization.
Signed-off-by: NErik Ekman <erik@kryo.se>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Convert pci/ioapic.c to be builtin only, with no module option, so we can
support IO-APIC hotplug.  Also make it depend on X86_IO_APIC.

[bhelgaas: changelog]
Signed-off-by: NYinghai Lu <yinghai@kernel.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Fix indent code style and replace 'MSI interrupt controller' of comment
with 'MSI controller' to fix the following checkpatch issues:

  ERROR: code indent should use tabs where possible
  WARNING: please, no spaces at the start of a line
  WARNING: line over 80 characters
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Use max_t() instead of max(resource_size_t,) in order to fix
the following checkpatch warning.

  WARNING: max() should probably be max_t(resource_size_t, SZ_64K, size)
  WARNING: max() should probably be max_t(resource_size_t, SZ_1M, size)
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>

The mvebu PCI host controller driver uses an emulated PCI-to-PCI bridge to
leverage the core PCI kernel enumeration logic to dynamically create and
remove the MBus windows needed to access the memory and I/O regions of each
PCI interface.

In the context of this PCI-to-PCI bridge emulation, the driver emulates
all reads and writes to the PCI bridge registers.  Upon a write to the
registers configuring the I/O base and limit, the driver was creating the
MBus window and calling pci_ioremap_io() to setup the mapping.

However, it turns out that accesses to these registers are made in an IRQ
disabled context, while pci_ioremap_io() is a potentially sleeping
function.  Not only this is wrong, but it is causing fairly loud warnings
at boot time when the appropriate kernel hacking options are enabled.

This patch solves this by moving the pci_ioremap_io() call to the startup
of the driver.  At this point, we don't know how many PCI interfaces will
be enabled, so we are simply remapping the entire PCI I/O space to virtual
addresses.  This is reasonable since this I/O space is limited to 1 MB in
size, and also because the MBus windows continue to be created in a dynamic
fashion only when devices need them.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

* pci/misc:
  PCI/checkpatch: Deprecate DEFINE_PCI_DEVICE_TABLE

* pci/msi:
  PCI/MSI: Make pci_enable_msi/msix() 'nvec' argument type as int
  PCI/MSI: Return -ENOSYS for unimplemented interfaces, not -1
  PCI/MSI: Return msix_capability_init() failure if populate_msi_sysfs() fails
  s390/PCI: Remove superfluous check of MSI type
  s390/PCI: Fix single MSI only check
  PCI/MSI: Export MSI mode using attributes, not kobjects

* pci/deletion:
  PCI/portdrv: Remove extra get_device()/put_device() for pcie_device
  PCI/portdrv: Add put_device() after device_register() failure
  PCI/portdrv: Cleanup error paths

* pci/host-designware:
  PCI: designware: Fix I/O transfers by using CPU (not realio) address
  PCI: designware: Add dw_pcie prefix before cfg_read/write
  PCI: designware: Fix missing MSI IRQs

* pci/host-mvebu:
  PCI: mvebu: Remove redundant of_match_ptr

* pci/host-imx6:
  PCI: imx6: Fix bugs in PCIe startup code
  PCI: imx6: Start link in Gen1 before negotiating for Gen2 mode
  PCI: imx6: Factor out link up wait loop
  PCI: imx6: Factor out PHY reset
  PCI: imx6: Report "link up" only after link training completes
  PCI: imx6: Make reset-gpio optional

Make pci_enable_msi_block(), pci_enable_msi_block_auto() and
pci_enable_msix() consistent with regard to the type of 'nvec' argument.
Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NTejun Heo <tj@kernel.org>

Suggested-by: NBen Hutchings <bhutchings@solarflare.com>
Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NTejun Heo <tj@kernel.org>

If populate_msi_sysfs() function failed msix_capability_init() must return
the error code, but it returns the success instead.  This update fixes the
described misbehaviour.
Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NTejun Heo <tj@kernel.org>

arch_setup_msi_irqs() hook can only be called from the generic MSI code
which ensures correct MSI type parameter.
Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>

Multiple MSIs have never been supported on s390 architecture, but the
platform code fails to report single MSI only.
Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>

pp->io_base, which is the input of the outbound IO address translation
unit, should be the CPU address.  It was incorrectly programmed to the
realio address.

We should pass global_io_offset rather than sys->io_offset to
pci_ioremap_io(), so we map the new window into the first available spot in
the Linux view of the I/O space.

We must also pass CPU address instead of realio address to pci_ioremap_io().

This patch fixes above issue.  It has been tested with Lecroy PTC in AIC
mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise.
Tested-by: NMohit Kumar <mohit.kumar@st.com>
Tested-by: NTim Harvey <tharvey@gateworks.com>
Signed-off-by: NPratyush Anand <pratyush.anand@st.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Marek Vasut <marex@denx.de
Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>

The cfg_read/write functions are DesignWare-specific.  Add dw_pcie prefix
to avoid collision in global name space.
Tested-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NPratyush Anand <pratyush.anand@st.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>

The interrupts were cleared after the IRQ handler was called.  This means
that new interrupts that occur after the handler handled the previous IRQ
but before the interrupt is cleared will be missed.
Tested-by: NMarek Vasut <marex@denx.de>
Tested-by: NMatthias Mann <m.mann@arkona-technologies.de>
Signed-off-by: NHarro Haan <hrhaan@gmail.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NMohit Kumar <mohit.kumar@st.com>
Cc: Richard Zhu <hong-xing.zhu@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Juergen Beisert <jbe@pengutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Sean Cross <xobs@kosagi.com>

The PCI MSI sysfs code is a mess with kobjects for things that don't really
need to be kobjects.  This patch creates attributes dynamically for the MSI
interrupts instead of using kobjects.

Note, this removes a directory from sysfs.  Old MSI kobjects:

  pci_device
     └── msi_irqs
         └── 40
             └── mode

New MSI attributes:

  pci_device
     └── msi_irqs
         └── 40

As there was only one file "mode" with the kobject model, the interrupt
number is now a file that returns the "mode" of the interrupt (msi vs.
msix).
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NNeil Horman <nhorman@tuxdriver.com>

Previously pcie_device_init() called get_device() if device_register() for
the new pcie_device succeeded, and remove_iter() called put_device() when
removing before unregistering the device.

But device_register() already increments the reference count in
device_add(), so we don't need to do it again here.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

This is required so that we give up the last reference to the device.
Removed the kfree() as put_device will result in release_pcie_device()
being called and hence the container of the device will be kfree'd.

[bhelgaas: fix conflict after my previous cleanup]
Signed-off-by: NLevente Kurusa <levex@linux.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Make the straightline path the normal no-error path.  Check for errors and
return them directly, instead of checking for success and putting the
normal path in an "if" body.

No functional change.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

mvebu_pcie_of_match_table is always compiled in.  Hence of_match_ptr is not
required.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

LTSSM shouldn't be set once in assert_core_reset().  Move peripheral reset
just before LTSSM start.
Signed-off-by: NRichard Zhu <r65037@freescale.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Frank Li <lznuaa@gmail.com>
Cc: Harro Haan <hrhaan@gmail.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Yinghai Lu <yinghai@kernel.org>

This patch first forces the link into Gen1 mode before starting up the link
and, only after the link is up, start negotiating possible Gen2 mode
operation.  This is because without such sequence, some PCIe switches are
not detected at all.
Signed-off-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Frank Li <lznuaa@gmail.com>
Cc: Harro Haan <hrhaan@gmail.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Yinghai Lu <yinghai@kernel.org>

Split the function that waits for the PCIe link to come up from the rest if
the host init function.  We will find this change useful in the subsequent
patch, since this will be called twice then.

No functional change.

[bhelgaas: remove useless "return;"]
Signed-off-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Frank Li <lznuaa@gmail.com>
Cc: Harro Haan <hrhaan@gmail.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Yinghai Lu <yinghai@kernel.org>

Split the PCIe PHY reset from the link up function to make the code a
little more structured.

No functional change.
Signed-off-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Frank Li <lznuaa@gmail.com>
Cc: Harro Haan <hrhaan@gmail.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Yinghai Lu <yinghai@kernel.org>

While waiting for the PHY to report the PCIe link is up, we might hit a
situation where the link training is still in progress, while the PHY
already reports the link is up.  Add additional check for this condition.
Signed-off-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Frank Li <lznuaa@gmail.com>
Cc: Harro Haan <hrhaan@gmail.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Yinghai Lu <yinghai@kernel.org>

Some boards do not have a PCIe reset GPIO.  To avoid probe failure on these
boards, make the reset GPIO optional as well.

[bhelgaas: whitespace fixes]
Signed-off-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Frank Li <lznuaa@gmail.com>
Cc: Harro Haan <hrhaan@gmail.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Yinghai Lu <yinghai@kernel.org>

* pci/vc:
  PCI: Rename PCI_VC_PORT_REG1/2 to PCI_VC_PORT_CAP1/2
  PCI: Add Virtual Channel to save/restore support
  PCI: Add support for save/restore of extended capabilities
  PCI: Add pci_wait_for_pending() (refactor pci_wait_for_pending_transaction())

* pci/pciehp:
  PCI: pciehp: Move Attention & Power Indicator support tests to accessors
  PCI: pciehp: Use symbolic constants for Slot Control fields
  PCI: pciehp: Use symbolic constants, not hard-coded bitmask
  PCI: pciehp: Simplify "Power Fault Detected" checking/clearing
  PCI: pciehp: Announce slot capabilities (slot #, button, LEDs, etc)
  PCI: pciehp: Make various functions void since they can't fail
  PCI: pciehp: Remove error checks when accessing PCIe Capability
  PCI: pciehp: Drop pciehp_readw()/pciehp_writew() wrappers

* pci/host-tegra:
  PCI: Disable Gen2 for Tegra20 and Tegra30

* pci/host-rcar:
  PCI: rcar: Add runtime PM support
  PCI: rcar: Fix rcar_pci_probe() return value check

* pci/host-mvebu:
  PCI: mvebu: Remove duplicate of_clk_get_by_name() call
  PCI: mvebu: Support a bridge with no IO port window
  PCI: mvebu: Obey bridge PCI_COMMAND_MEM and PCI_COMMAND_IO bits
  PCI: mvebu: Drop writes to bridge Secondary Status register

* pci/host-imx6:
  PCI: imx6: Remove unneeded 'goto err'
  PCI: imx6: Remove unneeded check of platform_get_resource()

* pci/host-designware:
  PCI: designware: Use typical "for" loop idiom
  PCI: designware: Remove redundant call to pci_write_config_word()
  PCI: designware: Fix crash in dw_msi_teardown_irq()