Document the global clock controller found on Qualcomm devices.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

If max77686 chip is instantiated from device tree, it is desirable to
have an OF clock provider to allow device tree based look-up of clocks.
This patch adds OF clock provider registration to the clk-max77686
driver.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0.  Add a clock ID for it so that
we can reference it in device trees.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings.  Default names will be used
when an input clock is not given.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NEmilio López <emilio@elopez.com.ar>

This commit implements support for the "module 0" type of clocks, as
used by MMC, IR, NAND, SATA and other components.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMike Turquette <mturquette@linaro.org>

This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMike Turquette <mturquette@linaro.org>

This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NMike Turquette <mturquette@linaro.org>

This patch adds support for accuracy retrieval on fixed clocks.
It also adds a new dt property called 'clock-accuracy' to define the clock
accuracy.

This can be usefull for oscillator (RC, crystal, ...) definitions which are
always given an accuracy characteristic.
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

In some use cases Zynq's FPGA clocks are used as static clock
generators for IP in the FPGA part of the SOC for which no Linux driver
exists and would control those clocks. To avoid automatic
gating of these clocks in such cases a new property - fclk-enable - is
added to the clock controller's DT description to accomodate such use
cases. It's value is a bitmask, where a set bit results in enabling
the corresponding FCLK through the clkc.

FPGA clocks are handled following the rules below:

If an FCLK is not enabled by bootloaders, that FCLK will be disabled in
Linux. Drivers can enable and control it through the CCF as usual.

If an FCLK is enabled by bootloaders AND the corresponding bit in the
'fclk-enable' DT property is set, that FCLK will be enabled by the clkc,
resulting in an off by one reference count for that clock. Ensuring it
will always be running.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add a driver for SILabs 570, 571, 598, 599 programmable oscillators.
The devices generate low-jitter clock signals and are reprogrammable via
an I2C interface.
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Device tree clock binding document for EMMA Mobile EV2 SMU,
And Common clock framework based implementation of it.
Following nodes are defined to describe clock tree.
- renesas,emev2-smu
- renesas,emev2-smu-clkdiv
- renesas,emev2-smu-gclk

These bindings are designed manually based on
 19UH0037EJ1000_SMU : System Management Unit User's Manual

So far, reparent is not implemented, and is fixed to index #0.
Clock tree description is not included, and should be provided
by device-tree.
Signed-off-by: NTakashi Yoshii <takasi-y@ops.dti.ne.jp>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

MSTP clocks are gate clocks controlled through a register that handles
up to 32 clocks. The register is often sparsely populated.

Those clocks are found on Renesas ARM SoCs.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

DIV6 clocks are divider gate clocks controlled through a single
register. The divider is expressed on 6 bits, hence the name, and can
take values from 1/1 to 1/64.

Those clocks are found on Renesas ARM SoCs.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are
too custom to be supported in a generic driver. Those clocks can be
divided in two categories:

- Fixed rate clocks with multiplier and divisor set according to boot
  mode configuration

- Custom divider clocks with SoC-specific divider values

This driver supports both.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

DDR3A/B, ARM and PA PLL controllers have clkod register bits for
configuring postdiv values. So use it instead of using fixed
post dividers for these pll controllers. Assume that if fixed-postdiv
attribute is not present, use clkod register value for pistdiv.

Also update the Documentation of bindings to reflect the same.

Cc: Mike Turquette <mturquette@linaro.org
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is
used to support the clock gate that enable/disable/status registers
are seperated.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>

The required properties are not named "div" and "mult",
but rather "clock-div" and "clock-mult".
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Implement clock support for Tegra124.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

This was tested on a NETGEAR ReadyNAS 2120 device (Marvell Armada XP
based board, via DT).
Signed-off-by: NArnaud Ebalard <arno@natisbad.org>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>

Add device tree support to the DW watchdog timer.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NJamie Iles <jamie@jamieiles.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-watchdog@vger.kernel.org

On CSR SiRFprimaII and SiRFatlasVI, the 6th timer can act as a watchdog
timer when the Watchdog mode is enabled.

watchdog occur when TIMER watchdog counter matches the value software
pre-set, when this event occurs, the effect is the same as the system
software reset.
Signed-off-by: NXianglong Du <Xianglong.Du@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Cc: Romain Izard <romain.izard.pro@gmail.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>

I accidently put the devicetree bindings for the MEN A21 watchdog driver in
Documentation/devicetree/bindings/gpio instead of
Documentation/devicetree/bindings/watchdog, this patch addresses this error.
Signed-off-by: NJohannes Thumshirn <johannes.thumshirn@men.de>
Acked-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: Rob Landley <rob@landley.net>

Add a driver for the watchdog timer found on Ralink SoC
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
Cc: linux-watchdog@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree-discuss@lists.ozlabs.org

This patch adds a watchdog driver for the main hardware watchdog timer
found on MOXA ART SoCs.

The MOXA ART SoC provides one writable timer register, restarting
the hardware once it reaches zero. The register is auto decremented
every APB clock cycle.
Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>

Introduce support for Broadcom Serial Controller (BSC) I2C bus found
in the Kona family of Mobile SoCs.  FIFO hardware is utilized but only
standard mode (100kHz), fast mode (400kHz), fast mode plus (1MHz), and
I2C high-speed (3.4 MHz) bus speeds are supported.
Signed-off-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMatt Porter <matt.porter@linaro.org>
Reviewed-by: NMarkus Mayer <markus.mayer@linaro.org>
[wsa: fixed Kconfig sorting, squashed broken out patches into one]
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Add documentation for the generic OMAP DES crypto modul describing the device
tree bindings.
Reviewed-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NJoel Fernandes <joelf@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

A new compatible property "ti,omap5-sham" is added to the omap-sham driver
recently to support SHA/MD5 for OMAP5,DRA7 and AM43XX. Documenting the
same.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add OF document for LM90 in Documentation/devicetree/.

[JD: Add this new file to the LM90 MAINTAINERS entry.]
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Correct the SPI node compatible property items to match example code and
match current DTS usage.
Signed-off-by: NEric Witcher <ewitcher@mindspring.com>
Acked-by: NSourav Poddar <sourav.poddar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch adds support to SSC (Synchronous Serial Controller)
I2C driver. This IP also supports SPI protocol, but this is not
the aim of this driver.

This IP is embedded in all ST SoCs for Set-top box platorms, and
supports I2C Standard and Fast modes.
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds
the device tree nodes for them.
Signed-off-by: NHongbo Zhang <hongbo.zhang@freescale.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

This patch updates the discription of each type of DMA controller and its
channels, it is preparation for adding another new DMA controller binding, it
also fixes some defects of indent for text alignment at the same time.
Signed-off-by: NHongbo Zhang <hongbo.zhang@freescale.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

This allows the charger to be enabled with devicetree, and allows the
parameters for charging the backup battery to be set.
Signed-off-by: NNeilBrown <neilb@suse.de>
Acked-by: NKumar Gala <galak@codeaurora.org>
Acked-by: NGrant Likely <grant.likely@linaro.org>
Signed-off-by: NAnton Vorontsov <anton@enomsg.org>

LP8555 is one of the LP855x family devices.

This device needs pre_init_device() and post_init_device() driver
structure.  It's same as LP8557, so the device configuration code is
shared with LP8557.  Backlight outputs are generated from dual DC-DC boost
converters.  It's configurable EPROM settings which are defined in the
platform data.

Driver documentation and device tree bindings are updated.
Signed-off-by: NMilo Kim <milo.kim@ti.com>
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Signed-off-by: NMischa Jonker <mjonker@synopsys.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NVineet Gupta <vgupta@synopsys.com>

Updated the number of LDOs and BUCKs as per the user manual.
Fixed trivial typos to improve readability.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Updated supported SoC name for pwm-samsung.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>