1. 18 6月, 2006 2 次提交
    • R
      [ARM] Replace extramask with a full copy of the sigmask · cc1a8521
      Russell King 提交于
      There's not much point in splitting the sigmask between two different
      locations, so copy it entirely into a proper sigset_t.  This will
      eventually allow rt_sigframe and sigframe to share more code.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      cc1a8521
    • R
      [ARM] Remove rt_sigframe puc and pinfo pointers · ce7a3fdc
      Russell King 提交于
      These two members appear to be surplus to requirements.  Discussing
      this issue with glibc folk:
      
      | > Additionally, do you see any need for these weird "puc" and "pinfo"
      | > pointers in the kernels rt_sigframe structure?  Can we kill them?
      |
      | We can kill them.  I checked with Phil B. about them last week, and he
      | didn't remember any reason they still needed to be there.  And nothing
      | should know where they are on the stack.  Unfortunately, doing this
      | will upset GDB, which knows that the saved registers are 0x88 bytes
      | above the stack pointer on entrance to an rt signal trampoline; but,
      | since puc and pinfo are quite recognizable, I can adapt GDB to support
      | the new layout if you want to remove them.
      
      So remove them.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      ce7a3fdc
  2. 17 5月, 2006 1 次提交
  3. 16 5月, 2006 2 次提交
  4. 10 5月, 2006 1 次提交
  5. 05 5月, 2006 1 次提交
  6. 24 4月, 2006 1 次提交
  7. 21 4月, 2006 2 次提交
  8. 11 4月, 2006 2 次提交
  9. 02 4月, 2006 1 次提交
    • L
      [ARM] 3439/2: xsc3: add I/O coherency support · 23759dc6
      Lennert Buytenhek 提交于
      Patch from Lennert Buytenhek
      
      This patch adds support for the I/O coherent cache available on the
      xsc3.  The approach is to provide a simple API to determine whether the
      chipset supports coherency by calling arch_is_coherent() and then
      setting the appropriate system memory PTE and PMD bits.  In addition,
      we call this API on dma_alloc_coherent() and dma_map_single() calls.
      A generic version exists that will compile out all the coherency-related
      code that is not needed on the majority of ARM systems.
      
      Note that we do not check for coherency in the dma_alloc_writecombine()
      function as that still requires a special PTE setting.  We also don't
      touch dma_mmap_coherent() as that is a special ARM-only API that is by
      definition only used on non-coherent system.
      Signed-off-by: NDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      23759dc6
  10. 01 4月, 2006 2 次提交
  11. 29 3月, 2006 1 次提交
  12. 27 3月, 2006 2 次提交
  13. 26 3月, 2006 2 次提交
  14. 24 3月, 2006 1 次提交
  15. 22 3月, 2006 7 次提交
  16. 16 3月, 2006 3 次提交
  17. 15 3月, 2006 1 次提交
  18. 13 3月, 2006 1 次提交
  19. 07 3月, 2006 1 次提交
    • T
      [PATCH] fix next_timer_interrupt() for hrtimer · 69239749
      Tony Lindgren 提交于
      Also from Thomas Gleixner <tglx@linutronix.de>
      
      Function next_timer_interrupt() got broken with a recent patch
      6ba1b912 as sys_nanosleep() was moved to
      hrtimer.  This broke things as next_timer_interrupt() did not check hrtimer
      tree for next event.
      
      Function next_timer_interrupt() is needed with dyntick (CONFIG_NO_IDLE_HZ,
      VST) implementations, as the system can be in idle when next hrtimer event
      was supposed to happen.  At least ARM and S390 currently use
      next_timer_interrupt().
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Russell King <rmk@arm.linux.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      69239749
  20. 23 2月, 2006 1 次提交
  21. 22 2月, 2006 1 次提交
  22. 17 2月, 2006 1 次提交
  23. 16 2月, 2006 1 次提交
    • R
      [ARM] Fix SMP initialisation oops · 7bbb7940
      Russell King 提交于
      A change to the SMP initialisation caused the following oops:
      
       CPU1: Booted secondary processor
       CPU1: D VIPT write-back cache
       CPU1: I cache: 32768 bytes, associativity 4, 32 byte lines, 256 sets
       CPU1: D cache: 32768 bytes, associativity 4, 32 byte lines, 256 sets
       <7>Calibrating delay loop... 83.14 BogoMIPS (lpj=415744)
       <1>Unable to handle kernel NULL pointer dereference at virtual address 0000001c
       ...
       PC is at enqueue_task+0x1c/0x64
       LR is at activate_task+0xcc/0xe4
      
      SMP initialisation now requires cpu_possible_map to be initialised in
      setup_arch().  Move this from smp_prepare_cpus() to smp_init_cpus()
      and call it from our setup_arch() if CONFIG_SMP is enabled.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      7bbb7940
  24. 09 2月, 2006 2 次提交