1. 11 2月, 2012 1 次提交
    • D
      drm/i915: fixup interlaced vertical timings confusion, part 1 · ca9bfa7e
      Daniel Vetter 提交于
      We have a pretty decent confusion about vertical timings of interlaced
      modes. Peter Ross has written a patch that makes interlace modes work
      on a lot more platforms/output combinations by doubling the vertical
      timings.
      
      The issue with that patch is that core drm _does_ support specifying
      whether we want these vertical timings in fields or frames, we just
      haven't managed to consistently use this facility. The relavant
      function is drm_mode_set_crtcinfo, which fills in the crtc timing
      information.
      
      The first thing to note is that the drm core keeps interlaced modes in
      frames, but displays modelines in fields. So when the crtc modeset
      helper copies over the mode into adjusted_mode it will already contain
      vertical timings in half-frames. The result is that the fixup code in
      intel_crtc_mode_fixup doesn't actually do anything (in most cases at
      least).
      
      Now gen3+ natively supports interlaced modes and wants the vertical
      timings in frames. Which is what sdvo already fixes up, at least under
      some conditions.
      
      There are a few other place that demand vertical timings in fields
      but never actually deal with interlaced modes, so use frame timings
      for consistency, too. These are:
      - lvds panel,
      - dvo encoders - dvo is the only way gen2 could support interlaced
        mode, but currently we don't support any encoders that do.
      - tv out - despite that the tv dac sends out an interlaced signal it
        expects a progressive mode pipe configuration.
      All these encoders enforce progressive modes by resetting
      interlace_allowed.
      
      Hence we always want crtc vertical timings in frames. Enforce this in
      our crtc mode_fixup function and rip out any redudant timing
      computations from the encoders' mode_fixup function.
      
      v2-4: Adjust the vertical timings a bit.
      
      v5: Split out the 'subtract-one for interlaced' fixes.
      
      v6: Clarify issues around tv-out and gen2.
      Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com>
      Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Tested-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Tested-by: NChristopher Egert <cme3000@gmail.com>
      Tested-by: NAlfonso Fiore <alfonso.fiore@gmail.com>
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      ca9bfa7e
  2. 07 1月, 2012 1 次提交
  3. 17 12月, 2011 2 次提交
  4. 01 11月, 2011 1 次提交
  5. 21 10月, 2011 5 次提交
  6. 22 9月, 2011 1 次提交
  7. 20 9月, 2011 1 次提交
  8. 05 6月, 2011 1 次提交
  9. 18 5月, 2011 1 次提交
    • C
      drm/i915/sdvo: Reorder i2c initialisation before ddc proxy · 56184e3d
      Chris Wilson 提交于
      The ddc proxy depends upon the underlying i2c bus being selected. Under
      certain configurations, the i2c-adapter functionality is queried during
      initialisation and so may trigger an OOPS during boot. Hence, we need to
      reorder the initialisation of the ddc proxy until after we hook up the i2c
      adapter for the SDVO device.
      
      The condition under which it fails is when the i2c_add_adapter calls
      into i2c_detect which will attempt to probe all valid addresses on the
      adapter iff there is a pre-existing i2c_driver with the same class as
      the freshly added i2c_adapter.
      
      So it appears to depend upon having compiled in (or loaded such a
      module before i915.ko) an i2c-driver that likes to futz over the
      i2c_adapters claiming DDC support.
      Reported-by: NMihai Moldovan <ionic@ionic.de>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NKeith Packard <keithp@keithp.com>
      Signed-off-by: NKeith Packard <keithp@keithp.com>
      56184e3d
  10. 23 2月, 2011 1 次提交
  11. 22 2月, 2011 1 次提交
  12. 11 2月, 2011 1 次提交
  13. 10 2月, 2011 1 次提交
  14. 26 1月, 2011 3 次提交
  15. 12 1月, 2011 1 次提交
  16. 23 12月, 2010 1 次提交
  17. 17 12月, 2010 1 次提交
  18. 10 12月, 2010 1 次提交
  19. 25 11月, 2010 1 次提交
  20. 24 11月, 2010 1 次提交
  21. 22 11月, 2010 1 次提交
  22. 22 10月, 2010 2 次提交
  23. 19 10月, 2010 1 次提交
  24. 28 9月, 2010 1 次提交
  25. 24 9月, 2010 2 次提交
  26. 21 9月, 2010 1 次提交
  27. 18 9月, 2010 1 次提交
    • C
      drm/i915: use GMBUS to manage i2c links · f899fc64
      Chris Wilson 提交于
      Use the GMBUS interface rather than direct bit banging to grab the EDID
      over DDC (and for other forms of auxiliary communication with external
      display controllers). The hope is that this method will be much faster
      and more reliable than bit banging for fetching EDIDs from buggy monitors
      or through switches, though we still preserve the bit banging as a
      fallback in case GMBUS fails.
      
      Based on an original patch by Jesse Barnes.
      
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      f899fc64
  28. 15 9月, 2010 4 次提交