1. 30 1月, 2008 21 次提交
  2. 20 10月, 2007 2 次提交
  3. 18 10月, 2007 2 次提交
    • J
      x86: multi-byte single instruction NOPs · 32c464f5
      Jan Beulich 提交于
      Add support for and use the multi-byte NOPs recently documented to be
      available on all PentiumPro and later processors.
      
      This patch only applies cleanly on top of the "x86: misc.
      constifications" patch sent earlier.
      
      [ tglx: arch/x86 adaptation ]
      Signed-off-by: NJan Beulich <jbeulich@novell.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      
       arch/x86/kernel/alternative.c  |   23 ++++++++++++++++++++++-
       include/asm-x86/processor_32.h |   22 ++++++++++++++++++++++
       include/asm-x86/processor_64.h |   22 ++++++++++++++++++++++
       3 files changed, 66 insertions(+), 1 deletion(-)
      32c464f5
    • S
      i386: fix argument signedness warnings · ffecad95
      Satyam Sharma 提交于
      These build warnings:
      
      In file included from include/asm/thread_info.h:16,
      from include/linux/thread_info.h:21,
      from include/linux/preempt.h:9,
      from include/linux/spinlock.h:49,
      from include/linux/vmalloc.h:4,
      from arch/i386/boot/compressed/misc.c:14:
      include/asm/processor.h: In function cpuid_count
      include/asm/processor.h:615: warning: pointer targets in passing argument 1 of native_cpuid differ in signedness
      include/asm/processor.h:615: warning: pointer targets in passing argument 2 of native_cpuid differ in signedness
      include/asm/processor.h:615: warning: pointer targets in passing argument 3 of native_cpuid differ in signedness
      include/asm/processor.h:615: warning: pointer targets in passing argument 4 of native_cpuid differ in signedness
      
      come because the arguments have been specified as pointers to (signed) int
      types, not unsigned. So let's specify those as unsigned. Do some codingstyle
      here and there while at it.
      
      [ tglx: arch/x86 adaptation ]
      Signed-off-by: NSatyam Sharma <satyam@infradead.org>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      ffecad95
  4. 11 10月, 2007 1 次提交
  5. 23 7月, 2007 1 次提交
    • J
      x86: Replace NSC/Cyrix specific chipset access macros by inlined functions. · f25f64ed
      Juergen Beisert 提交于
      Due to index register access ordering problems, when using macros a line
      like this fails (and does nothing):
      
      	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
      
      With inlined functions this line will work as expected.
      
      Note about a side effect: Seems on Geode GX1 based systems the
      "suspend on halt power saving feature" was never enabled due to this
      wrong macro expansion. With inlined functions it will be enabled, but
      this will stop the TSC when the CPU runs into a HLT instruction.
      Kernel output something like this:
      	Clocksource tsc unstable (delta = -472746897 ns)
      
      This is the 3rd version of this patch.
      
       - Adding missed arch/i386/kernel/cpu/mtrr/state.c
      	Thanks to Andres Salomon
       - Adding some big fat comments into the new header file
       	Suggested by Andi Kleen
      
      AK: fixed x86-64 compilation
      Signed-off-by: NJuergen Beisert <juergen@kreuzholzen.de>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      f25f64ed
  6. 22 7月, 2007 1 次提交
  7. 17 7月, 2007 1 次提交
  8. 13 7月, 2007 1 次提交
  9. 15 5月, 2007 1 次提交
  10. 03 5月, 2007 9 次提交