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  1. 08 6月, 2012 2 次提交
  3. 14 4月, 2012 1 次提交
  5. 10 4月, 2012 1 次提交
  7. 07 4月, 2012 2 次提交
  9. 06 4月, 2012 2 次提交
  11. 03 4月, 2012 1 次提交
  13. 01 4月, 2012 3 次提交
  15. 30 11月, 2011 1 次提交
  17. 24 11月, 2011 1 次提交
    • S
      ASoC: Tegra I2S: Remove dependency on pdev->id · d4a2eca7
      由 Stephen Warren 提交于 
      When devices are instantiated from device-tree, pdev->id is set to -1.
Rework the driver so it doesn't depend on the ID.

Tegra I2S instantiated from board files are configured with pdev
name "tegra-i2s" and ID 0 or 1. The driver core then names the
device "tegra-i2s.0" or "tegra-i2s.1". This is not changing.

When a device is instantiated from device-tree, it will have
pdev->name="" and pdev->id=-1. For this reason, the pdev->id value is
not something we can rely on.

This patch doesn't actually change any names though:

When a device is instantiated from device-tree, the overall device name
will be "${unit_address}.${node_name}". This causes issues such as
clk_get() failures due to lack of a device-name match. To solve that,
AUXDATA was invented, to force a specific device name, thus allowing
dev_name() to return the same as the non-device-tree case. Tegra
currently uses AUXDATA for the I2S controllers. Eventually, AUXDATA will
go away, most likely replaced by phandle-based references within the
device tree.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      d4a2eca7
  19. 23 11月, 2011 3 次提交
  21. 03 10月, 2011 1 次提交
  23. 04 7月, 2011 2 次提交
    • S
      ASoC: Tegra: I2S: s/clk_get_sys/clk_get/ · b5f9cfed
      由 Stephen Warren 提交于 
      The clock needed by the I2S driver is associated with the I2S device name
in the standard fashion. Hence, use clk_get(dev) instead of clk_get_sys(clk_name).
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      b5f9cfed
    • S
      ASoC: Tegra: I2S: Ensure clock is enabled when writing regs · 713d1369
      由 Stephen Warren 提交于 
      The I2S controller needs a clock to respond to register writes. Without
this, register writes will at worst hang the CPU. In practice, I've only
observed writes being dropped.

Luckily, the dropped register writes historically had no effect:

TEGRA_I2S_TIMING: The value we wrote was the reset default.

TEGRA_I2S_FIFO_SCR: The default was for the FIFOs to request more data
when one slot was empty. The requested value was for the FIFOs to request
when four slots were empty. The DMA controller in the mainline kernel is
configured to burst a single entry at a time into the FIFO, hence there
was no issue. The only negative effect was on bus efficiency losses due
to an increased number of arbitration attempts.

However, in various non-upstream changes, the DMA controller now bursts
four entries at a time into the FIFO. If there is only space for one
entry, the data is simply dropped. In practice, this resulted in 3/4 of
samples being dropped, and playback at 4x the expected rate and pitch.
By fixing the clocking issue, this is solved.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      713d1369
  25. 20 5月, 2011 1 次提交
  27. 14 2月, 2011 1 次提交
  29. 31 1月, 2011 1 次提交
  31. 13 1月, 2011 1 次提交
  33. 11 1月, 2011 2 次提交