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  1. 11 3月, 2016 11 次提交
    • M
      xtensa: support hardware breakpoints/watchpoints · c91e02bd
      由 Max Filippov 提交于 
      Use perf framework to manage hardware instruction and data breakpoints.
Add two new ptrace calls: PTRACE_GETHBPREGS and PTRACE_SETHBPREGS to
query and set instruction and data breakpoints.
Address bit 0 choose instruction (0) or data (1) break register, bits
31..1 are the register number.
Both calls transfer two 32-bit words: address (0) and control (1).
Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set.
Data breakpoint control word bit 31 is 'trigger on store', bit 30 is
'trigger on load, bits 29..0 are length. Length 0 is used to clear a
breakpoint. To set a breakpoint length must be a power of 2 in the range
1..64 and the address must be length-aligned.

Introduce new thread_info flag: TIF_DB_DISABLED. Set it if debug
exception is raised by the kernel code accessing watched userspace
address and disable corresponding data breakpoint. On exit to userspace
check that flag and, if set, restore all data breakpoints.

Handle debug exceptions raised with PS.EXCM set. This may happen when
window overflow/underflow handler or fast exception handler hits data
breakpoint, in which case save and disable all data breakpoints,
single-step faulting instruction and restore data breakpoints.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      c91e02bd
    • M
      xtensa: use context structure for debug exceptions · 6ec7026a
      由 Max Filippov 提交于 
      With implementation of data breakpoints debug exceptions raised when
PS.EXCM is set need to be handled, e.g. window overflow code can write
to watched userspace address. Currently debug exception handler uses
EXCSAVE and DEPC SRs to save temporary registers, but DEPC may not be
available when PS.EXCM is set and more space will be needed to save
additional state.
Reorganize debug context: create per-CPU structure debug_table instance
and store its address in the EXCSAVE<debug level> instead of
debug_exception function address. Expand this structure when more save
space is needed.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      6ec7026a
    • M
      xtensa: remove remaining non-functional KGDB bits · 816aa588
      由 Max Filippov 提交于 
      KGDB is not supported on xtensa, but there are bits of related code
under arch/xtensa/kernel. Remove these bits.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      816aa588
    • M
      xtensa: clear all DBREAKC registers on start · 7de7ac78
      由 Max Filippov 提交于 
      There are XCHAL_NUM_DBREAK registers, clear them all.
This also fixes cryptic assembler error message with binutils 2.25 when
XCHAL_NUM_DBREAK is 0:

  as: out of memory allocating 18446744073709551575 bytes after a total
  of 495616 bytes

Cc: stable@vger.kernel.org
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      7de7ac78
    • M
      xtensa: xtfpga: fix earlycon endianness · 56b9f9d6
      由 Max Filippov 提交于 
      Serial port is attached to XTFPGA boards as native endian device, now
that earlycon parameter parser understands mmio32native put it into
earlycon kernel parameter. This makes early console functional on both
little- and big-endian CPUs with identical kernel command lines.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      56b9f9d6
    • M
      xtensa: xtfpga: fix i2c controller register width and endianness · bce299ca
      由 Max Filippov 提交于 
      I2C controller is attached to XTFPGA boards as native endian device, mark
it as such in DTS.
Set register width in DTS to 4, this way it works both for little- and
big-endian CPUs.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      bce299ca
    • M
      xtensa: xtfpga: fix ethernet controller endianness · d99434e1
      由 Max Filippov 提交于 
      Ethernet controller is attached to XTFPGA boards as native endian device,
mark it as such in DTS and pass correct endianness in platform data.
This makes network functional on big-endian CPUs.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      d99434e1
    • M
      xtensa: xtfpga: fix serial port register width and endianness · abfbd895
      由 Max Filippov 提交于 
      Serial port is attached to XTFPGA boards as native endian device, mark
it as such in DTS and pass correct endianness in platform data.
Set register width in DTS to 4, this way it matches the platform data
and works correctly on big-endian CPUs.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      abfbd895
    • M
      xtensa: define CONFIG_CPU_{BIG,LITTLE}_ENDIAN · 4611bf7e
      由 Max Filippov 提交于 
      Query compiler for the CPU endianness and add corresponding definition
to KBUILD_CPPFLAGS. This allows using 'native-endian' property in DTS.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      4611bf7e
    • M
      xtensa: fix preemption in {clear,copy}_user_highpage · a67cc9aa
      由 Max Filippov 提交于 
      Disabling pagefault makes little sense there, preemption disabling is
what was meant.

Cc: stable@vger.kernel.org
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      a67cc9aa
    • M
      xtensa: ISS: don't hang if stdin EOF is reached · 362014c8
      由 Max Filippov 提交于 
      Simulator stdin may be connected to a file, when its end is reached
kernel hangs in infinite loop inside rs_poll, because simc_poll always
signals that descriptor 0 is readable and simc_read always returns 0.
Check simc_read return value and exit loop if it's not positive. Also
don't rewind polling timer if it's zero.

Cc: stable@vger.kernel.org
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      362014c8
  3. 21 1月, 2016 2 次提交
  5. 11 1月, 2016 4 次提交
  7. 10 1月, 2016 2 次提交
  9. 09 1月, 2016 14 次提交
  11. 08 1月, 2016 7 次提交