- 12 1月, 2011 3 次提交
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由 Jesse Barnes 提交于
Cleanup several aspects of the rc6 code: - misnamed intel_disable_clock_gating function (was only about rc6) - remove commented call to intel_disable_clock_gating - rc6 enabling code belongs in its own function (allows us to move the actual clock gating enable call back into restore_state) - allocate power & render contexts up front, only free on unload (avoids ugly lazy init at rc6 enable time) Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> [ickle: checkpatch cleanup] Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Jesse Barnes 提交于
Enabling RC6 implies setting a graphics context. Make sure we do that only after the ring has been enabled, otherwise our ring commands will hang. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
When bringing up new hardware, or otherwise experimenting, GPU hangs are a way of life. However, the automatic GPU reset can do more harm than good under these circumstances, as we may wish to capture a full trace for debugging. Based on a patch by Zhenyu Wang. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 05 1月, 2011 1 次提交
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由 Dave Airlie 提交于
We need to track the state of the switch in drivers, so that after s/r we don't resume the card we've explicitly switched off before. Also don't allow a userspace open to occur if we've switched the gpu off. Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 17 12月, 2010 1 次提交
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由 Mario Kleiner 提交于
v2: Change IS_IRONLAKE to IS_GEN5 to adapt to 2.6.37 This patch adds new functions for use by the drm core: .get_vblank_timestamp() provides a precise timestamp for the end of the most recent (or current) vblank interval of a given crtc, as needed for the DRI2 implementation of the OML_sync_control extension. It is a thin wrapper around the drm function drm_calc_vbltimestamp_from_scanoutpos() which does almost all the work. .get_scanout_position() provides the current horizontal and vertical video scanout position and "in vblank" status of a given crtc, as needed by the drm for use by drm_calc_vbltimestamp_from_scanoutpos(). The patch modifies the pageflip completion routine to use these precise vblank timestamps as the timestamps for pageflip completion events. This code has been only tested on a HP-Mini Netbook with Atom processor and Intel 945GME gpu. The codepath for (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) gpu's has not been tested so far due to lack of hardware. Signed-off-by: NMario Kleiner <mario.kleiner@tuebingen.mpg.de> Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 15 12月, 2010 1 次提交
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由 Yuanhan Liu 提交于
Add frame buffer compression on Sandybridge. The method is similar to Ironlake, except that two new registers of type GTTMMADR must be written with the right fence info. Signed-off-by: NYuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 10 12月, 2010 3 次提交
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由 Chris Wilson 提交于
Once we have read the value out of the GT power well, we need to remove the FORCE WAKE bit to allow the system to auto-power down. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
As suggested by Daniel Vetter, this is a safeguard should any of the registers cause reference to PTE entries. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
So we can remove the repeated initialisation. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 06 12月, 2010 1 次提交
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由 Chris Wilson 提交于
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 05 12月, 2010 2 次提交
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由 Chris Wilson 提交于
The bulk of the change is to convert the growing list of rings into an array so that the relationship between the rings and the semaphore sync registers can be easily computed. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
This will declare the machine wedged, but is better than truly wedging the machine. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 24 11月, 2010 1 次提交
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由 Daniel Vetter 提交于
This still uses the agp functions to actually reinstate the mappings (with a gross hack to make agp cooperate), but it wires everything up correctly for the switchover. The call to agp_rebind_memory can be dropped because all non-kms drivers do all their rebinding on EnterVT. v2: Be more paranoid and flush the chipset cache after restoring gtt mappings. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 22 11月, 2010 2 次提交
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由 Eric Anholt 提交于
This has proven sufficient to recover from a hang of the GPU using the gem_bad_blit test while at the KMS console then starting X. When attempting the same during an X session, the timer doesn't appear to trigger. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Eric Anholt 提交于
Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 19 11月, 2010 1 次提交
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由 Alex Shi 提交于
Frame buffer compression is broken on Ironlake due to buggy hardware. Currently it is disabled through chicken bits, but it still consumes over 1W more than if we simply never attempt to enable the FBC code paths. Signed-off-by: NAlex Shi <alex.shi@intel.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
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- 02 11月, 2010 1 次提交
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由 Chris Wilson 提交于
2.6.36 appears to respect the 0400 mode we assigned to the parameter preventing it from being adjusted after loading. However, this is safe to adjust at runtime. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31311Reported-by: NFernando Lemos <fernandotcl@gmail.com> Cc: stable@kernel.org Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 29 10月, 2010 1 次提交
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由 Chris Wilson 提交于
Eliminate the racy device unload by embedding a shrinker into each device. Smaller, simpler code. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 27 10月, 2010 1 次提交
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由 Chris Wilson 提交于
The ringbuffer keeps a pointer to the parent device, so we can use that instead of passing around the pointer on the stack. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 22 10月, 2010 2 次提交
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由 Chris Wilson 提交于
So remove the redundant bit in the capabilities block and s/IS_IRONLAKE/IS_GEN5/. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Based on an original patch by Zhenyu Wang, this initializes the BLT ring for SandyBridge and enables support for user execbuffers. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 01 10月, 2010 3 次提交
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由 Chris Wilson 提交于
The issue is that we may become stuck executing a long running shader and continually attempt to reset the GPU. (Or maybe we tickle some bug and need to break the vicious cycle.) So if we are detect a second hang within 5 seconds, give up trying to programme the GPU and report it wedged. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
So far only found registers for i830, i845, i865 and one of those has no effect on i865! At this moment in time, attempting to reset i8xx is a little optimistic... Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
When the GPU is reset, the fence registers are invalidated, so release the objects and clear them out. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 22 9月, 2010 1 次提交
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由 Chris Wilson 提交于
Otherwise we will hit a list handling assertion when moving the object to the inactive list. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 21 9月, 2010 11 次提交
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由 Chris Wilson 提交于
Suspending (especially hibernating) may take a finite amount of time, during which a hotplug event may trigger and we will attempt to handle it with inconsistent state. Disable hotplug polling around suspend and resume. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30070Reported-by: NRui Tiago Matos <tiagomatos@gmail.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Xiang, Haihao 提交于
This ring buffer is used for video decoding/encoding on Sandybridge. Signed-off-by: NXiang, Haihao <haihao.xiang@intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Xiang, Haihao 提交于
Signed-off-by: NXiang, Haihao <haihao.xiang@intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Previously we only tidied up the active bo lists for chipsets were we would attempt to reset the GPU. However, this action is necessary for the system to continue and reclaim the dead bo for all chipsets. Pointed out, in passing, by Owain Ainsworth. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Clear the GPU read domain for the inactive objects on a reset so that they are correctly invalidated on reuse. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Owain Ainsworth noticed that the reset code failed to clear the flushing list leaving the driver in an inconsistent state following a hung GPU. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
On more recent chipsets, restoring the display is not as simple as writing a few registers, so force a full modeset of the current configuration in order to retrain the display link. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Kenneth Graunke 提交于
Ironlake's graphics reset register has to be accessed via the MCHBAR, rather than via PCI config space, which requires some refactoring. Signed-off-by: NKenneth Graunke <kenneth@whitecape.org> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Kenneth Graunke 提交于
The graphics domains are listed as GRDOM in the documentation, and the GDRST PCI config register (0xc0) is only valid on I965 and GM45. Newer chips (like Sandy Bridge) have a different GDRST. Signed-off-by: NKenneth Graunke <kenneth@whitecape.org> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Kenneth Graunke 提交于
Previously, it was only being set if passed GDRST_FULL - but the only caller passed GDRST_RENDER. So the hardware never actually reset. The comments also did not match the code. Instead, just set the reset bit regardless of what flags were passed. The GPU now resets correctly on my GM45. Signed-off-by: NKenneth Graunke <kenneth@whitecape.org> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Avoid confusion between i965g meaning broadwater and the gen4+ chipset families. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 17 9月, 2010 1 次提交
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由 Chris Wilson 提交于
There is a second revision of B43 (a desktop gen4 part) floating around, functionally equivalent to the original B43, so simply add the new PCI-IDs. Bugzilla: https://bugs.freedesktop.org/show_bugs.cgi?id=30221Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
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- 16 9月, 2010 1 次提交
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由 Arnd Bergmann 提交于
The drm device drivers currently allow seeking on the character device but never care about the actual file position. When we change the default llseek operation to be no_llseek, calling llseek on a drm device would return an error condition, which is an API change. Explicitly setting noop_llseek lets us keep the current API. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Cc: David Airlie <airlied@linux.ie> Cc: dri-devel@lists.freedesktop.org
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- 08 9月, 2010 2 次提交
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由 Chris Wilson 提交于
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Chris Wilson 提交于
It is recommended that we use the Video BIOS tables that were copied into the OpRegion during POST when initialising the driver. This saves us from having to furtle around inside the ROM ourselves and possibly allows the vBIOS to adjust the tables prior to initialisation. On some systems, such as the Samsung N210, there is no accessible VBIOS and the only means of finding the VBT is through the OpRegion. v2: Rearrange the code so that ASLE is enabled along with ACPI v3: Enable OpRegion parsing even without ACPI Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Garrett <mjg@redhat.com>
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