- 31 7月, 2015 6 次提交
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由 Michal Simek 提交于
Enable watchdog on ep108. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Add usb nodes to DTSI and enable both of them on ep108. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Add SMMU DT node to DTSI. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Also enable can0 for ep108. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
The patch: "gpio: Added support to Zynq Ultrascale+ MPSoC" (sha1: bdf7a4ae) added zynqmp specific features. This patch is switching the driver to use the zynqmp compatible string. Also enable the driver for ep108 platform. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Suneel Garapati 提交于
add sata node with sata fixed clock nodes in dtsi file. enable sata in zynqmp-ep108.dts with broken-gen2. Signed-off-by: NSuneel Garapati <suneel.garapati@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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- 02 7月, 2015 1 次提交
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由 Y Vo 提交于
Add standby domain gpio controller for APM X-Gene SoC platform. Signed-off-by: NY Vo <yvo@apm.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKevin Hilman <khilman@linaro.org>
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- 12 6月, 2015 1 次提交
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由 Linus Walleij 提交于
The Juno board has two keys connected to a PL061 GPIO block, in accordance to DDI0524B "ARM Versatile Express Juno Development Platform" revision 1.0, table 2-4 "GPIO (0) and GPIO (1) used for additional user key entry". By trial-and-error I found that these are connected to the two keys named "power" and "home" on the motherboard. Register the GPIO block and these two keys in the device tree using the PL061 GPIO driver and the generic gpio keys. - Map POWER, HOME, VOL+ and VOL- to the obvious input events. - Map RLOCK to KEY_SCREENLOCK/KEY_COFFEE unless someone can explain better what this is for. - Map the NMI button to KEY_SYSREQ as this is used like so in the SYSREQ debugging hack. Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKevin Hilman <khilman@linaro.org>
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- 06 6月, 2015 1 次提交
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由 Duc Dang 提交于
There is a single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports. Signed-off-by: NDuc Dang <dhdang@apm.com> Signed-off-by: NTanmay Inamdar <tinamdar@apm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
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- 05 6月, 2015 1 次提交
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由 Bintian Wang 提交于
Add initial dtsi file to support Hisilicon Hi6220 SoC with support of Octal core CPUs in two clusters and each cluster has quard Cortex-A53. Also add dts file to support HiKey development board which based on Hi6220 SoC. Signed-off-by: NBintian Wang <bintian.wang@huawei.com> Acked-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: NYiping Xu <xuyiping@hisilicon.com> Tested-by: NWill Deacon <will.deacon@arm.com> Tested-by: NTyler Baker <tyler.baker@linaro.org> Tested-by: NKevin Hilman <khilman@linaro.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
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- 01 6月, 2015 2 次提交
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由 Yingjoe Chen 提交于
Model name in mt8173-evb.dts doesn't follow dts convention (it should be human readable model name). Fix it. Fixes: b3a37248 ("arm64: dts: Add mediatek MT8173 SoC and evaluation board dts and Makefile") Cc: <stable@vger.kernel.org> # v4.0+ Signed-off-by: NYingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
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由 Daniel Kurtz 提交于
Fix indentation nits to make mt8173.dtsi more consistent. Signed-off-by: NEddie Huang <eddie.huang@mediatek.com> Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
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- 29 5月, 2015 1 次提交
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由 Loc Ho 提交于
Add APM X-Gene SoC EDAC DTS entries. Signed-off-by: NLoc Ho <lho@apm.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: dougthompson@xmission.com Cc: ijc+devicetree@hellion.org.uk Cc: jcm@redhat.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mark.rutland@arm.com Cc: mchehab@osg.samsung.com Cc: patches@apm.com Cc: robh+dt@kernel.org Link: http://lkml.kernel.org/r/1432337580-3750-6-git-send-email-lho@apm.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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- 22 5月, 2015 5 次提交
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由 Liviu Dudau 提交于
This board is based on Juno r0 with updated Cortex A5x revisions and board errata fixes. It also contains coherent ThinLinks ports on the expansion slot that allow for an AXI master on the daughter card to participate in a coherency domain. Support for SoC PCIe host bridge will be added as a separate series. Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com> Acked-by: NJon Medhurst <tixy@linaro.org> Acked-by: NSudeep Holla <sudeep.holla@arm.com>
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由 Liviu Dudau 提交于
Juno contains a GICv2m extension for handling PCIe MSI messages. Add a node declaring the first frame of the extension. Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com> Acked-by: NJon Medhurst <tixy@linaro.org> Acked-by: NSudeep Holla <sudeep.holla@arm.com>
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由 Liviu Dudau 提交于
Juno based boards have a memory mapped timer @ 0x2a810000. This is disabled on r0 version of the board due to an SoC errata. Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com> Acked-by: NJon Medhurst <tixy@linaro.org> Acked-by: NSudeep Holla <sudeep.holla@arm.com>
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由 Liviu Dudau 提交于
Prepare the device tree for adding more boards based on Juno r0. Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com> Acked-by: NJon Medhurst <tixy@linaro.org> Acked-by: NSudeep Holla <sudeep.holla@arm.com>
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由 Liviu Dudau 提交于
During the review of the Juno DT files I've noticed that the GIC node label had two digits swapped leading to a different address being shown in the /sys/devices fs. Sudeep also pointed that public revisions of the Juno documentation list a different frequency for the FAXI system than what the one I've been using when creating the DT file. Verified with the firmware people to be the correct value in the shipped systems. Reported-by: NSudeep Holla <sudeep.holla@arm.com> Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com> Acked-by: NSudeep Holla <sudeep.holla@arm.com> Acked-by: NJon Medhurst <tixy@linaro.org>
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- 12 5月, 2015 2 次提交
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由 Mark Rutland 提交于
While skeleton.dtsi was initially conceived as a simple way to bootstrap writing a dts, it has proven to be problematic: * The #address-cells and #size-cells values used in skeleton.dtsi may not match what a user wants (e.g. when they need to describe a range larger than 4GB). * For dts files where memory nodes have unit-addresses, it adds a redundant /memory node, for which the reg entry may not be appropriately sized (e.g. where #size-cells has been overridden). * For dts files which assume that a bootloader will fill in the memory node(s), no node is present in the dts (and hence there is no attached comment), making it hard to distinguish these cases from bad dts files, and masking any warnings dtc may produce w.r.t. missing nodes. * The default empty /chosen and /aliases are somewhat useless, and it would be preferable for dts to fill these in (e.g. for /aliases/serial0 and /chosen/stdout-path). This patch removes skeleton.dtsi from arm64. There are currently no users, so we can remove it before any appear. Signed-off-by: NMark Rutland <mark.rutland@arm.com> Acked-by: NRob Herring <rob.herring@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Olof Johansson <olof@lixom.net> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Sudeep Holla 提交于
The clock generator in IOFPGA generates the two source clocks: 32kHz and 1MHz for the SP810 System Controller. The SP810 System Controller selects 32kHz or 1MHz as the sources for TIM_CLK[3:0], the SP804 timer clocks. The powerup default is 32kHz but the maximum of "refclk" and "timclk" is chosen by the SP810 driver. This patch adds support for SP810 system controller and also fixes the SP804 timer clock frequency. However the SP804 driver needs to be enabled on ARM64 to test this, which requires SP804 driver to be moved out of arch/arm. Fixes: 71f867ec ("arm64: Add Juno board device tree.") Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: NSudeep Holla <sudeep.holla@arm.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 11 5月, 2015 1 次提交
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由 Linus Walleij 提交于
This defines the Juno "APB system registers" as a syscon device, and all the LEDs controlled by the APB system registers right below it using the syscon LEDs driver on top of syscon. Define LED0 for heartbeat, LED1 for MMC0 activity and the following four LEDs indicating CPU activity using the Linux-specific DT bindings for triggers. This is the pattern and same drivers as used on the legacy platform device trees for the ARM Integrators and the RealView PB1176. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Tested-by: NLiviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 04 5月, 2015 1 次提交
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由 Yingjoe Chen 提交于
The 8173 pinctrl node doesn't follow dts convention. Fix them. Also add a comment to explain pinctrl register usage to make it more clear. Signed-off-by: NYingjoe Chen <yingjoe.chen@mediatek.com> Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
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- 28 4月, 2015 4 次提交
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由 Ivan T. Ivanov 提交于
Add initial device configuration nodes for APQ8016 and PM8916 GPIO's. Signed-off-by: NIvan T. Ivanov <ivan.ivanov@linaro.org> Signed-off-by: NKumar Gala <galak@codeaurora.org>
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由 Ivan T. Ivanov 提交于
Add the restart node so we can reboot the device. Signed-off-by: NIvan T. Ivanov <ivan.ivanov@linaro.org> Signed-off-by: NKumar Gala <galak@codeaurora.org>
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由 Ivan T. Ivanov 提交于
PM9816 has 2 SPMI devices per physical package. Add PMIC configuration nodes including sub-function device nodes and include them in boards, which are using 8x16 based chipset. PM9816 sub-function devices include: * GPIO block, with 4 pins * MPP block, with 4 pins * Volatage ADC (VADC), with multiple inputs * Thermal sensor device, which is using on chip VADC channel report PMIC die temperature. * Power key device, which is responsible for clean system reboot or shutdown * RTC device Signed-off-by: NIvan T. Ivanov <ivan.ivanov@linaro.org> Signed-off-by: NKumar Gala <galak@codeaurora.org>
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由 Ivan T. Ivanov 提交于
Add SPMI PMIC Arbiter configuration nodes for MSM8916. Signed-off-by: NIvan T. Ivanov <ivan.ivanov@linaro.org> Signed-off-by: NKumar Gala <galak@codeaurora.org>
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- 04 4月, 2015 4 次提交
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由 Will Deacon 提交于
Make the Juno .dts robust against potential reordering of the CPU nodes by adding an explicit interrupt-affinity property to the PMU node. While we're at it, fix the PMU interrupts numbers too. Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: NLiviu Dudau <liviu.dudau@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Kumar Gala 提交于
Add initial device tree support for Qualcomm APQ8016 SBC Evaluation board. This board is also referred to as the DragonBoard 410c. Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Kumar Gala 提交于
Add initial device tree support for Qualcomm MSM8916 SoC and MTP8916 evaluation board. At the current time we only boot up a single processor. Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Chunyan Zhang 提交于
Support only for ETF, FUNNEL, STM are included currently. Support for ETM, TPIU and the replicator linked to it are not included in this version patch. Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 02 4月, 2015 1 次提交
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由 Rameshwar Prasad Sahu 提交于
This patch adds the device tree node for APM X-Gene SoC DMA controller and DMA clock. Signed-off-by: NRameshwar Prasad Sahu <rsahu@apm.com> Signed-off-by: NLoc Ho <lho@apm.com> Signed-off-by: NVinod Koul <vinod.koul@intel.com>
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- 30 3月, 2015 1 次提交
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由 Dave Martin 提交于
The UART reference clock speed is 7273.8 kHz, not 72738 kHz. Dots aren't usually used in node names even though ePAPR permits them. However, this can easily be avoided by expressing the frequency in Hz, not kHz. This patch changes the name to refclk7273800hz, reflecting the actual clock speed. Signed-off-by: NDave Martin <Dave.Martin@arm.com> Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 28 3月, 2015 1 次提交
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由 Iyappan Subramanian 提交于
Signed-off-by: NIyappan Subramanian <isubramanian@apm.com> Signed-off-by: NKeyur Chudgar <kchudgar@apm.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 19 3月, 2015 1 次提交
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由 Keyur Chudgar 提交于
- Added new SGMII node for port 1 - Added port-id field Signed-off-by: NKeyur Chudgar <kchudgar@apm.com> Signed-off-by: NIyappan Subramanian <isubramanian@apm.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 12 3月, 2015 2 次提交
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由 Zhizhou Zhang 提交于
Adds the device tree support for Spreadtrum SC9836 SoC which is based on Sharkl64 platform. Sharkl64 platform contains the common nodes of Spreadtrum's arm64-based SoCs. Signed-off-by: NZhizhou Zhang <zhizhou.zhang@spreadtrum.com> Signed-off-by: NOrson Zhai <orson.zhai@spreadtrum.com> Signed-off-by: NChunyan Zhang <chunyan.zhang@spreadtrum.com> Acked-by: NMark Rutland <mark.rutland@arm.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Michal Simek 提交于
Initial version of device tree for Xilinx ZynqMP SoC. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NSören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 10 3月, 2015 1 次提交
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由 Hongzhou Yang 提交于
Add pinctrl, GPIO and EINT node to mt8173.dtsi. Signed-off-by: NHongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
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- 05 3月, 2015 1 次提交
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由 Iyappan Subramanian 提交于
This patch fixes the backward compatibility of the older driver with the newer firmware by making the binding unique so that the older driver won't recognize the non-supported interfaces. The new bindings are in sync with the newer firmware. Signed-off-by: NIyappan Subramanian <isubramanian@apm.com> Signed-off-by: NKeyur Chudgar <kchudgar@apm.com> Tested-by: NMark Langsdorf <mlangsdo@redhat.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 26 2月, 2015 1 次提交
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由 Sudeep Holla 提交于
Commit 5d425c18 ("arm64: kernel: add support for cpu cache information") adds cacheinfo support for ARM64. Since there's no architectural way of detecting the cpus that share particular cache, device tree can be used and the core cacheinfo already supports the same. This patch adds the L2 cache topology on Juno board, FVP/RTSM and foundation models. Signed-off-by: NSudeep Holla <sudeep.holla@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 28 1月, 2015 1 次提交
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由 Bhupesh Sharma 提交于
This patch adds the device tree support for FSL LS2085A SoC based on ARMv8 architecture. Following levels of DTSI/DTS files have been created for the LS2085A SoC family: - fsl-ls2085a.dtsi: DTS-Include file for FSL LS2085A SoC. - fsl-ls2085a-simu.dts: DTS file for FSL LS2085a software simulator model. In addition, this patch adds build support for FSL's LS2085A simulator model in arm64 dts Makefile. Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: NArnab Basu <arnab_basu@rocketmail.com> Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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