This allows us to remove the init_time callback in the DT machine
descriptors, shrinking the code.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Nobody is using these mappings so just drop them. of_iomap() in
the timer driver will take care of it for us. Doing this allows
us to remove the 8x60 and 8960 iomap files completely.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for msm as well.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Convert all GIC DT initialization over to use common irqchip_init
function.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>

Now that the GIC initialization sets up the handle_arch_irq pointer, we
can remove it for all machines and make it static.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Anton Vorontsov <avorontsov@mvista.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Now that the only field in struct sys_timer is .init, delete the struct,
and replace the machine descriptor .timer field with the initialization
function itself.

This will enable moving timer drivers into drivers/clocksource without
having to place a public prototype of each struct sys_timer object into
include/linux; the intent is to create a single of_clocksource_init()
function that determines which timer driver to initialize by scanning
the device dtree, much like the proposed irqchip_init() at:
http://www.spinics.net/lists/arm-kernel/msg203686.html

Includes mach-omap2 fixes from Igor Grinberg.
Tested-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

No real need to have a separate core.h from the common.h file.  Fold
these two prototypes into the common header file.

Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Consolidate the handful of iomapping functions into common.h so
that board files don't need to include mach/msm_iomap.h if they
don't need static virtual mapping addresses.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Rename this file to signify that this board is only supported via
devicetree.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

We don't plan to support anything besides devicetree on these
targets so remove all other machine support.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Add the timer entry and point the machine descriptor to the
device tree based msm timer.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
[davidb@codeaurora.org: Remove leading zeros]
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

The timer code relies on #defines from mach/iomap.h, cpu_is_*()
checks, and a global irq #define. All this makes this file
impossible to compile in a mult-target build. Therefore, make a
sys_timer struct for each SoC so that machine descriptors can
reference the correct timer. Then go through and replace all the
defines with raw values that are passed to a common
initialization function.

This paves the way to adding DT support to this code as well as
allows us to compile this file on multiple targets at the same
time.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

The MSM code has some antiquated register writes to set up the
PPIs to be edge triggered. Now that we have the percpu irq
interface we don't need this code so let's remove it and update
the percpu irq user (msm_timer) to set the irq type.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Commit 041f777c (ARM: msm: convert SMP platforms to
CONFIG_MULTI_IRQ_HANDLER, 2011-09-06) forgot to add the
.handle_irq for the DT machine record. Add it so we get
interrupts instead of panics on DT enabled bootloaders.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

A previous patch[1] added code to initialize an FPGA register on the
8660 "SURF" development platform.  Since this development platform is
not widely available, and there is now a more available device "the
Dragonboard" based on the same core SOC, this change was dropped.

However, the DT code kept a lingering call to this FPGA init function.
Remove it.

[1] https://lkml.org/lkml/2011/8/12/357Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NDavid Brown <davidb@codeaurora.org>

As of

    commit 75294957
    Author: Grant Likely <grant.likely@secretlab.ca>
    Date:   Tue Feb 14 14:06:57 2012 -0700

        irq_domain: Remove 'new' irq_domain in favour of the ppc one

the ARM gic controller uses proper irq domains.  Fix the MSM gic
initialization and DT so that it works again.
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>

irq_domain_add_simple() was a stop-gap measure until complete irq_domain
support was complete.  This patch removes the irq_domain_add_simple()
interface.

This patch also drops the explicit irq_domain initialization performed
by the mach-versatile code because the versatile interrupt controller
already has irq_domain support built into it.  This was a bug that was
hanging around quietly for a while, but with the full irq_domain which
actually verifies that irq_domain ranges are available it would cause
the registration to fail and the system wouldn't boot.

v4: Fixed number of irqs in mx5 gpio code
v2: Updated to pass in host_data pointer on irq_domain allocation.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Milton Miller <miltonm@bga.com>
Cc: Russell King <linux@arm.linux.org.uk>
Tested-by: NOlof Johansson <olof@lixom.net>

Convert the SMP msm platforms to be using the gic_handle_irq
function as their primary interrupt handler.
Tested-by: NDavid Brown <davidb@codeaurora.org>
Acked-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

After 0744a3ee (ARM: platform fixups: remove mdesc argument to
fixup function, 2010-12-20) the fixup functions introduced in
9e775ad1 (ARM: 7012/1: Set proper TEXT_OFFSET for newer MSMs,
2011-08-12) cause warnings like:

arch/arm/mach-msm/board-msm8x60.c:85: warning: initialization
from incompatible pointer type

Fix them by removing the machine_desc argument from the fixup
functions.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).

Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.

This also allows the removal of some duplicated code.

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: NDavid Brown <davidb@codeaurora.org>
Tested-by: NDavid Brown <davidb@codeaurora.org>
Tested-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Adds support for booting via device tree with a simple serial console.

Change-Id: I7f175b8db21928cd13e0fb49f3eed74966a2696f
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

MSMs post 8x50 have 2Mb at the beginning of RAM reserved for
shared memory. Since the kernel hasn't typically been told this
RAM exists, PHYS_OFFSET has been set to 0xN0200000 and the memory
atags passed to the kernel have matched. This doesn't play nicely
with things such as AUTO_ZRELADDR, which doesn't work at all, and
dynamic phys to virt, which requires an MSM specific workaround.

Work around these issues by telling the kernel RAM starts at
0xN0000000 (it actually does) and fixup the atags from the
bootloader (if necessary) to say the same. In addition, make sure
to set TEXT_OFFSET at least 2Mb beyond the start of RAM so that
the kernel doesn't end up being decompressed into shared memory.

After doing this, AUTO_ZRELADDR should work on MSM with no
problems and ARM_PATCH_PHYS_VIRT_16BIT should no longer be
necessary.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Convert to the new function names. Automated with coccinelle.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

This code is dead or otherwise useless so just remove it.
Reviewed-by: NSaravana Kannan <skannan@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt.  Move this into the common GIC code.
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Tested-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Provide gic_init() which initializes the GIC distributor and current
CPU's GIC interface for the boot (or single) CPU.
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Tested-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The MSM8X60 FFA contains different components than the MSM8X60 SURF,
and therefore requires a different ARCH type and machine ID.
Signed-off-by: NGregory Bean <gbean@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Board configuration for MSM8X60 simulation.
Signed-off-by: NSteve Muckle <smuckle@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Signed-off-by: NSteve Muckle <smuckle@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Private Peripheral interrupts could be edge triggered or level triggered
depending on the platform. Initialize handlers for these in board file.
Signed-off-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

On RUMI platform STIs are not enabled by default, contrary to the
GIC spec. The bits for STIs in the enable/enable clear registers
are also RW instead of RO. STIs need to be enabled at initialization
time.
Signed-off-by: NSteve Muckle <smuckle@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Board configuration for MSM8X60 emulation on RUMI3.
Signed-off-by: NSteve Muckle <smuckle@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Add the 'gpiomux' api, which addresses the following shortcomings
of existing tlmm api:

- gpio power-collapse, which is managed by a peripheral processor on
  other targets, must be managed by the application processor on the 8x60.
- The enable/disable flag of the legacy gpio_tlmm_config api
  is not applicable on the 8x60, and causes confusion.
- The gpio 'direction' bits are meaningless for all func_sel
  configurations except for generic-gpio mode (func_sel 0), in which
  case the gpio_direction_* functions should be used.  Having these
  bits in the tlmm api leads to confusion and misuse of the gpiolib
  api, and they have been removed in gpiomux.
- The functional api of the legacy system ran contrary to the typical
  use-case, which is a single massive configuration at boot.  Rather
  than forcing hundreds of 'config' function calls, the new api
  allows data to be configured with a single table.

gpiomux_get and gpiomux_put are meant to be called automatically
when gpio_request and gpio_free are called, giving automatic
gpiomux/tlmm control to those drivers/lines with simple
power profiles - in the simplest cases, an entry in the gpiomux table
and the correct usage of gpiolib is all that is required to get proper
gpio power control.
Signed-off-by: NGregory Bean <gbean@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

kbuild explicitly includes this at build time.
Signed-off-by: NDave Jones <davej@redhat.com>

Base patch for PA6T and PA6T-1682M. This introduces the
arch/powerpc/platform/pasemi directory, together with basic
implementations for various setup.

Much of this was based on other platform code, i.e. Maple, etc.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This is a patch for the Hilscher netx builtin ethernet ports. The
netx board support was merged into 2.6.17-git2.
The netx is a arm926 based SoC.
Signed-off-by: NRobert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

--
 drivers/net/Kconfig             |   11
 drivers/net/Makefile            |    1
 drivers/net/netx-eth.c          |  516 ++++++++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-netx/eth.h |   27 ++
 4 files changed, 555 insertions(+)
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Patch from Sascha Hauer

This patch adds the base support for Hilscher's netX network
processors.
Signed-off-by: NRobert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Sascha Hauer

This patch adds framebuffer support for Hilscher's netX network
processors.
Signed-off-by: NRobert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from SAN People

Following changes were made to clock.c:

1) Replaced <asm/hardware/clock.h> with <linux/clk.h>
2) Removed old unused clk_enable & clk_disable.
3) Replaced clk_use/clk_unuse with clk_enable/clk_disable.

Otherwise it's the same as the previous patch.
Signed-off-by: NAndrew Victor <andrew@sanpeople.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>