1. 18 4月, 2008 2 次提交
  2. 31 3月, 2008 1 次提交
  3. 05 3月, 2008 1 次提交
  4. 07 2月, 2008 2 次提交
    • D
      async_tx: replace 'int_en' with operation preparation flags · d4c56f97
      Dan Williams 提交于
      Pass a full set of flags to drivers' per-operation 'prep' routines.
      Currently the only flag passed is DMA_PREP_INTERRUPT.  The expectation is
      that arch-specific async_tx_find_channel() implementations can exploit this
      capability to find the best channel for an operation.
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      Acked-by: NShannon Nelson <shannon.nelson@intel.com>
      Reviewed-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>
      d4c56f97
    • D
      async_tx: kill tx_set_src and tx_set_dest methods · 0036731c
      Dan Williams 提交于
      The tx_set_src and tx_set_dest methods were originally implemented to allow
      an array of addresses to be passed down from async_xor to the dmaengine
      driver while minimizing stack overhead.  Removing these methods allows
      drivers to have all transaction parameters available at 'prep' time, saves
      two function pointers in struct dma_async_tx_descriptor, and reduces the
      number of indirect branches..
      
      A consequence of moving this data to the 'prep' routine is that
      multi-source routines like async_xor need temporary storage to convert an
      array of linear addresses into an array of dma addresses.  In order to keep
      the same stack footprint of the previous implementation the input array is
      reused as storage for the dma addresses.  This requires that
      sizeof(dma_addr_t) be less than or equal to sizeof(void *).  As a
      consequence CONFIG_DMADEVICES now depends on !CONFIG_HIGHMEM64G.  It also
      requires that drivers be able to make descriptor resources available when
      the 'prep' routine is polled.
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      Acked-by: NShannon Nelson <shannon.nelson@intel.com>
      0036731c
  5. 03 2月, 2008 1 次提交
  6. 25 1月, 2008 1 次提交
  7. 13 7月, 2007 2 次提交
    • D
      dmaengine: make clients responsible for managing channels · d379b01e
      Dan Williams 提交于
      The current implementation assumes that a channel will only be used by one
      client at a time.  In order to enable channel sharing the dmaengine core is
      changed to a model where clients subscribe to channel-available-events.
      Instead of tracking how many channels a client wants and how many it has
      received the core just broadcasts the available channels and lets the
      clients optionally take a reference.  The core learns about the clients'
      needs at dma_event_callback time.
      
      In support of multiple operation types, clients can specify a capability
      mask to only be notified of channels that satisfy a certain set of
      capabilities.
      
      Changelog:
      * removed DMA_TX_ARRAY_INIT, no longer needed
      * dma_client_chan_free -> dma_chan_release: switch to global reference
        counting only at device unregistration time, before it was also happening
        at client unregistration time
      * clients now return dma_state_client to dmaengine (ack, dup, nak)
      * checkpatch.pl fixes
      * fixup merge with git-ioat
      
      Cc: Chris Leech <christopher.leech@intel.com>
      Signed-off-by: NShannon Nelson <shannon.nelson@intel.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      Acked-by: NDavid S. Miller <davem@davemloft.net>
      d379b01e
    • D
      dmaengine: refactor dmaengine around dma_async_tx_descriptor · 7405f74b
      Dan Williams 提交于
      The current dmaengine interface defines mutliple routines per operation,
      i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc.  Adding
      more operation types (xor, crc, etc) to this model would result in an
      unmanageable number of method permutations.
      
      	Are we really going to add a set of hooks for each DMA engine
      	whizbang feature?
      		- Jeff Garzik
      
      The descriptor creation process is refactored using the new common
      dma_async_tx_descriptor structure.  Instead of per driver
      do_<operation>_<dest>_to_<src> methods, drivers integrate
      dma_async_tx_descriptor into their private software descriptor and then
      define a 'prep' routine per operation.  The prep routine allocates a
      descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
      are valid.  Descriptor creation and submission becomes:
      
      struct dma_device *dev;
      struct dma_chan *chan;
      struct dma_async_tx_descriptor *tx;
      
      tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
      tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
      tx->tx_set_dest(dma_addr_t, tx, index)
      tx->tx_submit(tx)
      
      In addition to the refactoring, dma_async_tx_descriptor also lays the
      groundwork for definining cross-channel-operation dependencies, and a
      callback facility for asynchronous notification of operation completion.
      
      Changelog:
      * drop dma mapping methods, suggested by Chris Leech
      * fix ioat_dma_dependency_added, also caught by Andrew Morton
      * fix dma_sync_wait, change from Andrew Morton
      * uninline large functions, change from Andrew Morton
      * add tx->callback = NULL to dmaengine calls to interoperate with async_tx
        calls
      * hookup ioat_tx_submit
      * convert channel capabilities to a 'cpumask_t like' bitmap
      * removed DMA_TX_ARRAY_INIT, no longer needed
      * checkpatch.pl fixes
      * make set_src, set_dest, and tx_submit descriptor specific methods
      * fixup git-ioat merge
      * move group_list and phys to dma_async_tx_descriptor
      
      Cc: Jeff Garzik <jeff@garzik.org>
      Cc: Chris Leech <christopher.leech@intel.com>
      Signed-off-by: NShannon Nelson <shannon.nelson@intel.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      Acked-by: NDavid S. Miller <davem@davemloft.net>
      7405f74b
  8. 04 7月, 2006 1 次提交
  9. 28 6月, 2006 1 次提交
  10. 18 6月, 2006 2 次提交