Instead of, wrongly, reusing the 'val' variable, use a dedicated
one for reading the status register.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Fix compilation warning by typecasting the tx_buf pointer.

[I'm not thrilled with resorting to a cast; but I cannot see a better
way to go about this.  I don't want to drop the const from struct
spi_transfer ~~glikely]
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

For small transfers at high speeds the expected transfer time can easily
be well under 1ms, causing the delay in wait_for_xfer() to be only the
dead reckoning fudge factor of 5ms currently included. Experiments on
some of my systems shows that this is marginal for some transfers so
double it to 10ms.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Allow the use of the S3C64xx SPI controller with things like PMICs by
moving the init up to subsys_initcall().
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NJassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The S3C64xx SPI driver requires the machine to call s3c64xx_spi_set_info()
to select a few options, including the clock to use for the SPI controller.
If this is not done then a NULL will be passed as the clock name for
clk_get(), causing an obscure crash. Guard against this and other missing
configuration by validating that the clock name has been filled in in
the platform data that ets passed in.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

String constants that are continued on subsequent lines with \
are not good.
Signed-off-by: NJoe Perches <joe@perches.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Since most of the chip-selects are simply going to be like
gpio_set_value, it would do good to have the same callback type
so that it could simply be made to point at gpio_set_value.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Header for platform specific stuff has been rename to include the SoC
type. Include the new header instead.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Add precautionary check before releasing memory region.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The pointer to SPI rate source clock had better be the member of
driver local data structure rather than platform specific.
Also, remove definitions of variable 'sci' that are rendered
useless as a consequence.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The instance of SPI clock for controller and that used for generating
signals ought to be independently handled.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Rename 'struct s3c64xx_spi_cntrlr_info' to lesser wordy
'struct s3c64xx_spi_info'
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Each SPI controller has exactly one CS line and as such doesn't
provide for multi-cs. We implement a workaround to support
multi-cs by _not_ configuring the mux'ed CS pin for each SPI
controller. The CS mechanism is assumed to be fully machine
specific - the driver doesn't even assume some GPIO pin is used
to control the CS.

The driver selects between DMA and POLLING mode depending upon
the xfer size - DMA mode for xfers bigger than FIFO size, POLLING
mode otherwise.

The driver has been designed to be capable of running SoCs since
s3c64xx and till date, for that reason some of the register fields
have been passed via, SoC specific, platform data.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>