1. 19 2月, 2016 1 次提交
  2. 17 2月, 2016 1 次提交
    • A
      spi: imx: allow only WML aligned transfers to use DMA · 390f0ffe
      Anton Bondarenko 提交于
      RX DMA tail data handling doesn't work correctly in many cases with current
      implementation. It happens because SPI core was setup to generates both RX
      and RX TAIL events. And RX TAIL event does not work correctly.
      This can be easily verified by sending SPI transaction with size modulus
      WML(32 in our case) not equal 0.
      
      Also removing change introduced in f6ee9b58
      since this change only fix usecases with transfer size from 33 to 128 bytes
      and doesn't fix 129 bytes and bigger.
      
      This is output from transaction with len 138 bytes in loopback mode at 10Mhz:
      TX0000: a3 97 a2 55 53 be f1 fc f9 79 6b 52 14 13 e9 e2
      TX0010: 2d 51 8e 1f 56 08 57 27 a7 05 d4 d0 52 82 77 75
      TX0020: 1b 99 4a ed 58 3d 6a 52 36 d5 24 4a 68 8e ad 95
      TX0030: 5f 3c 35 b5 c4 8c dd 6c 11 32 3d e2 b4 b4 59 cf
      TX0040: ce 23 3d 27 df a7 f9 96 fc 1e e0 66 2c 0e 7b 8c
      TX0050: ca 30 42 8f bc 9f 7b ce d1 b8 b1 87 ec 8a d6 bb
      TX0060: 2e 15 63 0e 3c dc a4 3a 7a 06 20 a7 93 1b 34 dd
      TX0070: 4c f5 ec 88 96 68 d6 68 a0 09 6f 8e 93 47 c9 41
      TX0080: db ac cf 97 89 f3 51 05 79 71
      
      RX0000: a3 97 a2 55 53 be f1 fc f9 79 6b 52 14 13 e9 e2
      RX0010: 2d 51 8e 1f 56 08 57 27 a7 05 d4 d0 52 82 77 75
      RX0020: 1b 99 4a ed 58 3d 6a 52 36 d5 24 4a 68 8e ad 95
      RX0030: 5f 3c 35 00 00 b5 00 00 00 c4 00 00 8c 00 00 dd
      RX0040: 6c 11 32 3d e2 b4 b4 59 cf ce 23 3d 27 df a7 f9
      RX0050: 96 fc 1e e0 66 2c 0e 7b 8c ca 30 42 8f 1f 1f bc
      RX0060: 9f 7b ce d1 b8 b1 87 ec 8a d6 bb 2e 15 63 0e ed
      RX0070: ed 3c 58 58 58 dc 3d 3d a4 6a 6a 3a 52 52 7a 36
      RX0080: 06 20 a7 93 1b 34 dd 4c f5 ec
      
      Zeros at offset 33 and 34 caused by reading empty RX FIFO which not possible
      if DMA RX read was triggered by RX event. This mean DMA was triggered
      by RX TAIL event.
      Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
      Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      390f0ffe
  3. 23 1月, 2016 1 次提交
  4. 16 12月, 2015 4 次提交
  5. 08 12月, 2015 4 次提交
  6. 04 12月, 2015 1 次提交
  7. 23 10月, 2015 1 次提交
    • A
      spi: imx: fix ecspi mode setup · 1476253c
      Andrew Y. Kuksov 提交于
      Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3
      
      SPI_MODE_0 and SPI_MODE_1 requires clock low when inactive. SPI_MODE_2
      and SPI_MODE_3 requires clk high when inactive.
      Currently driver can just set bits in fields SCLK_PHA (SPI Clock/Data
      Phase Control), SCLK_POL (SPI Clock Polarity Control),
      SCLK_CTL (controls the inactive state of SCLK) ans SS_POL (SPI SS
      Polarity Select) of ECSPIx_CONFIGREG register.
      This patch allows driver to clear corresponding bits in these fields.
      Signed-off-by: NAndrew Y. Kuksov <qxovxp@gmail.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      1476253c
  8. 24 7月, 2015 1 次提交
    • S
      spi: imx: Fix small DMA transfers · f6ee9b58
      Sascha Hauer 提交于
      DMA transfers must be greater than the watermark level size. spi_imx->rx_wml
      and spi_imx->tx_wml contain the watermark level in 32bit words whereas struct
      spi_transfer contains the transfer len in bytes. Fix the check if DMA is
      possible for a transfer accordingly. This fixes transfers with sizes between
      33 and 128 bytes for which previously was claimed that DMA is possible.
      
      Fixes: f62caccd (spi: spi-imx: add DMA support)
      Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      Cc: stable@vger.kernel.org
      Signed-off-by: NMark Brown <broonie@kernel.org>
      f6ee9b58
  9. 02 5月, 2015 1 次提交
  10. 02 4月, 2015 1 次提交
    • L
      spi: imx: read back the RX/TX watermark levels earlier · f511ab09
      Lucas Stach 提交于
      They are used to decide if the controller can do DMA on a buffer
      of a specific length and thus are needed before any transfer is attempted.
      
      This fixes a memory leak where the SPI core uses the drivers can_dma()
      callback to determine if a buffer needs to be mapped. As the watermark
      levels aren't correct at that point the driver falsely claims to be able to
      DMA the buffer when it fact it isn't.
      After the transfer has been done the core uses the same callback to
      determine if it needs to unmap the buffers. As the driver now correctly
      claims to not being able to DMA the buffer the core doesn't attempt to
      unmap the buffer which leaves the SGT leaking.
      
      Fixes: f62caccd (spi: spi-imx: add DMA support)
      Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      Cc: stable@vger.kernel.org
      f511ab09
  11. 03 3月, 2015 1 次提交
  12. 05 2月, 2015 1 次提交
  13. 03 2月, 2015 1 次提交
  14. 30 12月, 2014 1 次提交
  15. 20 10月, 2014 1 次提交
  16. 18 9月, 2014 1 次提交
  17. 28 2月, 2014 1 次提交
    • P
      spi: spi-imx: spi_imx_remove: do not disable disabled clocks · fd40dccb
      Philippe De Muyter 提交于
      Currently, at module removal, one gets the following warnings:
      ------------[ cut here ]------------
      WARNING: at drivers/clk/clk.c:780 clk_disable+0x18/0x24()
      Modules linked in: spi_imx(-) [last unloaded: ev76c560]
      CPU: 1 PID: 16337 Comm: rmmod Tainted: G        W    3.10.17-80548-g90191eb-dirty #33
      [<80013b4c>] (unwind_backtrace+0x0/0xf8) from [<800115dc>] (show_stack+0x10/0x14)
      [<800115dc>] (show_stack+0x10/0x14) from [<800257b8>] (warn_slowpath_common+0x4c/0x68)
      [<800257b8>] (warn_slowpath_common+0x4c/0x68) from [<800257f0>] (warn_slowpath_null+0x1c/0x24)
      [<800257f0>] (warn_slowpath_null+0x1c/0x24) from [<803f60ec>] (clk_disable+0x18/0x24)
      [<803f60ec>] (clk_disable+0x18/0x24) from [<7f02c9cc>] (spi_imx_remove+0x54/0x9c [spi_imx])
      [<7f02c9cc>] (spi_imx_remove+0x54/0x9c [spi_imx]) from [<8025868c>] (platform_drv_remove+0x18/0x1c)
      [<8025868c>] (platform_drv_remove+0x18/0x1c) from [<80256f60>] (__device_release_driver+0x70/0xcc)
      [<80256f60>] (__device_release_driver+0x70/0xcc) from [<80257770>] (driver_detach+0xcc/0xd0)
      [<80257770>] (driver_detach+0xcc/0xd0) from [<80256d90>] (bus_remove_driver+0x7c/0xc0)
      [<80256d90>] (bus_remove_driver+0x7c/0xc0) from [<80068668>] (SyS_delete_module+0x144/0x1f8)
      [<80068668>] (SyS_delete_module+0x144/0x1f8) from [<8000e080>] (ret_fast_syscall+0x0/0x30)
      ---[ end trace 1f5df9ad54996300 ]---
      ------------[ cut here ]------------
      WARNING: at drivers/clk/clk.c:780 clk_disable+0x18/0x24()
      Modules linked in: spi_imx(-) [last unloaded: ev76c560]
      CPU: 1 PID: 16337 Comm: rmmod Tainted: G        W    3.10.17-80548-g90191eb-dirty #33
      [<80013b4c>] (unwind_backtrace+0x0/0xf8) from [<800115dc>] (show_stack+0x10/0x14)
      [<800115dc>] (show_stack+0x10/0x14) from [<800257b8>] (warn_slowpath_common+0x4c/0x68)
      [<800257b8>] (warn_slowpath_common+0x4c/0x68) from [<800257f0>] (warn_slowpath_null+0x1c/0x24)
      [<800257f0>] (warn_slowpath_null+0x1c/0x24) from [<803f60ec>] (clk_disable+0x18/0x24)
      [<803f60ec>] (clk_disable+0x18/0x24) from [<7f02c9e8>] (spi_imx_remove+0x70/0x9c [spi_imx])
      [<7f02c9e8>] (spi_imx_remove+0x70/0x9c [spi_imx]) from [<8025868c>] (platform_drv_remove+0x18/0x1c)
      [<8025868c>] (platform_drv_remove+0x18/0x1c) from [<80256f60>] (__device_release_driver+0x70/0xcc)
      [<80256f60>] (__device_release_driver+0x70/0xcc) from [<80257770>] (driver_detach+0xcc/0xd0)
      [<80257770>] (driver_detach+0xcc/0xd0) from [<80256d90>] (bus_remove_driver+0x7c/0xc0)
      [<80256d90>] (bus_remove_driver+0x7c/0xc0) from [<80068668>] (SyS_delete_module+0x144/0x1f8)
      [<80068668>] (SyS_delete_module+0x144/0x1f8) from [<8000e080>] (ret_fast_syscall+0x0/0x30)
      ---[ end trace 1f5df9ad54996301 ]---
      
      Since commit 9e556dcc, "spi: spi-imx: only
      enable the clocks when we start to transfer a message", clocks are always
      disabled except when transmitting messages.  There is thus no need to
      disable them at module removal.
      
      Fixes: 9e556dcc (spi: spi-imx: only enable the clocks when we start to transfer a message)
      Signed-off-by: NPhilippe De Muyter <phdm@macqel.be>
      Acked-by: NHuang Shijie <b32955@freescale.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      Cc: stable@vger.kernel.org
      fd40dccb
  18. 23 2月, 2014 1 次提交
  19. 15 2月, 2014 1 次提交
  20. 10 2月, 2014 1 次提交
  21. 03 2月, 2014 1 次提交
  22. 20 12月, 2013 1 次提交
    • M
      spi: spi-imx: Fix out-of-order CS/SCLK operation at low speeds · 6fd8b850
      Marek Vasut 提交于
      Problem:
      --------
       The problem this patch addresses has the following assumptions about the
       SPI bus setup:
       - The hardware used to find this is Freescale i.MX537 @ 1200MHz
       - The SPI SCLK operate at very low speed, less than 200 kHz
       - There are two SPI devices attached to the bus
         - Each device uses different GPIO for chipselect
         - Each device requires different SCLK signal polarity
      
       The observation of the SCLK and GPIO chipselect lines with a logic analyzer
       shows, that the SCLK polarity change does sometimes happen after the GPIO
       chipselect is asserted. The SPI slave device reacts on that by counting the
       SCLK polarity change as a clock pulse, which disrupts the communication with
       the SPI slave device.
      
      Explanation:
      ------------
       We found an interesting correlation, that the maximum delay between the write
       into the ECSPIx_CONFIGREG register and the change of SCLK polarity at each
       SCLK frequency of 10 kHz, 20 kHz, 50 kHz and 100 kHz is 100 uS, 50 uS, 20 uS
       and 10 uS respectively. This lead us to a theory, that at SCLK frequency of
       1 Hz, the delay would be 1 S. Therefore, the time it takes for the write to
       ECSPIx_CONFIGREG to take effect in the hardware is up to the duration of 1
       tick of the SCLK clock.
      
       During this delay period, if the SCLK frequency is too low, the execution of
       the spi-imx.c driver can advance so much, that the GPIO chipselect will be
       asserted. The GPIO chipselect is asserted almost immediatelly.
      
      Solution:
      ---------
       The solution this patch presents is simple. We calculate the resulting SCLK
       clock first by dividing the ECSPI block clock by both dividers that are to be
       programmed into the configuration register. Based on the resulting SCLK clock,
       we derive the delay it will take for the changes to get really applied. We are
       extra careful here so we delay twice as long as we should. Note that the patch
       does not create additional overhead at high speeds as the delay will likely be
       close to zero there.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      To: linux-spi@vger.kernel.org
      Cc: Fabio Estevam <fabio.estevam@freescale.com>
      Cc: Huang Shijie <b32955@freescale.com>
      Cc: Mark Brown <broonie@kernel.org>
      Cc: Sascha Hauer <s.hauer@pengutronix.de>
      Cc: Shawn Guo <shawn.guo@linaro.org>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      6fd8b850
  23. 23 10月, 2013 1 次提交
  24. 07 10月, 2013 1 次提交
    • A
      spi: bitbang: Let spi_bitbang_start() take a reference to master · 702a4879
      Axel Lin 提交于
      Many drivers that use bitbang library have a leak on probe error paths.
      This is because once a spi_master_get() call succeeds, we need an additional
      spi_master_put() call to free the memory.
      
      Fix this issue by moving the code taking a reference to master to
      spi_bitbang_start(), so spi_bitbang_start() will take a reference to master on
      success. With this change, the caller is responsible for calling
      spi_bitbang_stop() to decrement the reference and spi_master_put() as
      counterpart of spi_alloc_master() to prevent a memory leak.
      
      So now we have below patten for drivers using bitbang library:
      
      probe:
      spi_alloc_master        -> Init reference count to 1
      spi_bitbang_start       -> Increment reference count
      remove:
      spi_bitbang_stop        -> Decrement reference count
      spi_master_put          -> Decrement reference count (reference count reaches 0)
      
      Fixup all users accordingly.
      Signed-off-by: NAxel Lin <axel.lin@ingics.com>
      Suggested-by: NUwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
      Acked-by: NUwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      702a4879
  25. 17 9月, 2013 1 次提交
    • A
      spi: bitbang: Let spi_bitbang_start() take a reference to master · 94c69f76
      Axel Lin 提交于
      Many drivers that use bitbang library have a leak on probe error paths.
      This is because once a spi_master_get() call succeeds, we need an additional
      spi_master_put() call to free the memory.
      
      Fix this issue by moving the code taking a reference to master to
      spi_bitbang_start(), so spi_bitbang_start() will take a reference to master on
      success. With this change, the caller is responsible for calling
      spi_bitbang_stop() to decrement the reference and spi_master_put() as
      counterpart of spi_alloc_master() to prevent a memory leak.
      
      So now we have below patten for drivers using bitbang library:
      
      probe:
      spi_alloc_master        -> Init reference count to 1
      spi_bitbang_start       -> Increment reference count
      remove:
      spi_bitbang_stop        -> Decrement reference count
      spi_master_put          -> Decrement reference count (reference count reaches 0)
      
      Fixup all users accordingly.
      Signed-off-by: NAxel Lin <axel.lin@ingics.com>
      Suggested-by: NUwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
      Acked-by: NUwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      94c69f76
  26. 29 7月, 2013 1 次提交
  27. 15 7月, 2013 2 次提交
  28. 30 5月, 2013 2 次提交
  29. 13 5月, 2013 2 次提交
  30. 05 2月, 2013 1 次提交
  31. 08 12月, 2012 1 次提交