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      [ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counter · 838ccbc3
      Nicolas Pitre 提交于
      This is done in a completely lockless fashion. Bits 0 to 31 of the count
      are provided by the hardware while bits 32 to 62 are stored in memory.
      The top bit in memory is used to synchronize with the hardware count
      half-period.  When the top bit of both counters (hardware and in memory)
      differ then the memory is updated with a new value, incrementing it when
      the hardware counter wraps around.  Because a word store in memory is
      atomic then the incremented value will always be in synch with the top
      bit indicating to any potential concurrent reader if the value in memory
      is up to date or not wrt the needed increment.  And any race in updating
      the value in memory is harmless as the same value would be stored more
      than once.
      Signed-off-by: NNicolas Pitre <nico@cam.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      838ccbc3