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  1. 17 3月, 2014 1 次提交
  3. 03 3月, 2014 1 次提交
  5. 02 3月, 2014 1 次提交
    • L
      iio:adc: Add Xilinx XADC driver · bdc8cda1
      由 Lars-Peter Clausen 提交于 
      The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx.
The XADC has a DRP interface for communication. Currently two different
frontends for the DRP interface exist. One that is only available on the ZYNQ
family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
on all series 7 platforms and is a softmacro with a AXI interface. This driver
supports both interfaces and internally has a small abstraction layer that hides
the specifics of these interfaces from the main driver logic.

The ADC has a couple of internal channels which are used for voltage and
temperature monitoring of the FPGA as well as one primary and up to 16 channels
auxiliary channels for measuring external voltages. The external auxiliary
channels can either be directly connected each to one physical pin on the FPGA
or they can make use of an external multiplexer which is responsible for
multiplexing the external signals onto one pair of physical pins.

The voltage and temperature monitoring channels also have an event capability
which allows to generate a interrupt when their value falls below or raises
above a set threshold.

Buffered sampling mode is supported by the driver, but only for AXI-XADC since
the ZYNQ XADC interface does not have capabilities for supporting buffer mode
(no end-of-conversion interrupt). If buffered mode is supported the driver will
register two triggers. One "xadc-samplerate" trigger which will generate samples
with the configured samplerate. And one "xadc-convst" trigger which will
generate one sample each time the CONVST (conversion start) signal is asserted.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      bdc8cda1
  7. 18 2月, 2014 1 次提交
  9. 15 2月, 2014 1 次提交
  11. 08 2月, 2014 1 次提交
  13. 04 2月, 2014 1 次提交
  15. 11 1月, 2014 2 次提交
  17. 07 1月, 2014 4 次提交
    • S
      mfd: input: iio: ti_amm335x: Rework TSC/ADC synchronization · 7ca6740c
      由 Sebastian Andrzej Siewior 提交于 
      The ADC driver always programs all possible ADC values and discards
them except for the value IIO asked for. On the am335x-evm the driver
programs four values and it takes 500us to gather them. Reducing the number
of conversations down to the (required) one also reduces the busy loop down
to 125us.

This leads to another error, namely the FIFOCOUNT register is sometimes
(like one out of 10 attempts) not updated in time leading to EBUSY.
The next read has the FIFOCOUNT register updated.
Checking for the ADCSTAT register for being idle isn't a good choice either.
The problem is that if TSC is used at the same time, the HW completes the
conversation for ADC *and* before the driver noticed it, the HW begins to
perform a TSC conversation and so the driver never seen the HW idle. The
next time we would have two values in the FIFO but since the driver reads
everything we always see the current one.
So instead of polling for the IDLE bit in ADCStatus register, we should
check the FIFOCOUNT register. It should be one instead of zero because we
request one value.

This change in turn leads to another error. Sometimes if TSC & ADC are
used together the TSC starts generating interrupts even if nobody
actually touched the touchscreen. The interrupts seem valid because TSC's
FIFO is filled with values for each channel of the TSC. This condition stops
after a few ADC reads but will occur again. Not good.

On top of this (even without the changes I just mentioned) there is a ADC
& TSC lockup condition which was reported to me by Jeff Lance including the
following test case:
A busy loop of "cat /sys/bus/iio/devices/iio\:device0/in_voltage4_raw"
and a mug on touch screen. With this setup, the hardware will lockup after
something between 20 minutes and it could take up to a couple of hours.
During that lockup, the ADCSTAT register says 0x30 (or 0x70) which means
STEP_ID = IDLE and FSM_BUSY = yes. That means the hardware says that it is
idle and busy at the same time which is an invalid condition.

For all this reasons I decided to rework this TSC/ADC part and add a
handshake / synchronization here:
First the ADC signals that it needs the HW and writes a 0 mask into the
SE register. The HW (if active) will complete the current conversation
and become idle. The TSC driver will gather the values from the FIFO
(woken up by an interrupt) and won't "enable" another conversation.
Instead it will wake up the ADC driver which is already waiting. The ADC
driver will start "its" conversation and once it is done, it will
enable the TSC steps so the TSC will work again.

After this rework I haven't observed the lockup so far. Plus the busy
loop has been reduced from 500us to 125us.

The continues-read mode remains unchanged.
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Acked-by: NJonathan Cameron <jic23@kernel.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
      7ca6740c
    • S
      mfd: ti_am335x: Drop am335x_tsc_se_update() from resume path · 3954b7bf
      由 Sebastian Andrzej Siewior 提交于 
      The update of the SE register in MFD doesn't look right as it has
nothing to do with it. The better place to do it is in TSC driver (which
is already doing it) and in the ADC driver which needs this only in the
continues mode.
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Acked-by: NJonathan Cameron <jic23@kernel.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
      3954b7bf
    • S
      mfd: ti_am335x_tscadc: Don't read back REG_SE · 7e170c6e
      由 Sebastian Andrzej Siewior 提交于 
      The purpose of reg_se_cache has been defeated. It should avoid the
read-back of the register to avoid the latency and the fact that the
bits are reset to 0 after the individual conversation took place.

The reason why this is required like this to work, is that read-back of
the register removes the bits of the ADC so they do not start another
conversation after the register is re-written from the TSC side for the
update.
To avoid the not required read-back I introduce a "set once" variant which
does not update the cache mask. After the conversation completes, the
bit is removed from the SE register anyway and we don't plan a new
conversation "any time soon". The current set function is renamed to
set_cache to distinguish the two operations.
This is a small preparation for a larger sync-rework.
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Acked-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: NJonathan Cameron <jic23@kernel.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
      7e170c6e
    • S
      iio: ti_am335x_adc: Adjust the closing bracket in tiadc_read_raw() · fb7f8ce3
      由 Sebastian Andrzej Siewior 提交于 
      It somehow looks like the ending bracket belongs to the if statement but
it does belong to the while loop. This patch moves the bracket where it
belongs.
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Acked-by: NJonathan Cameron <jic23@kernel.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
      fb7f8ce3
  19. 19 12月, 2013 1 次提交
  21. 18 12月, 2013 1 次提交
  23. 08 12月, 2013 1 次提交
  25. 04 12月, 2013 1 次提交
  27. 25 11月, 2013 2 次提交
  29. 15 11月, 2013 1 次提交
  31. 09 11月, 2013 2 次提交
  33. 06 11月, 2013 1 次提交
  35. 02 11月, 2013 1 次提交
  37. 24 10月, 2013 4 次提交
  39. 21 10月, 2013 1 次提交
  41. 19 10月, 2013 3 次提交
  43. 18 10月, 2013 1 次提交
    • J
      iio: at91: introduce touch screen support in iio adc driver · c8b11de0
      由 Josh Wu 提交于 
      AT91 ADC hardware integrate touch screen support. So this patch add touch
screen support for at91 adc iio driver.
To enable touch screen support in adc, you need to add the dt parameters:
  1. which type of touch are used? (4 or 5 wires), sample period time.
  2. correct pressure detect threshold value.

In the meantime, since touch screen will use a interal period trigger of adc,
so it is conflict to other hardware triggers. Driver will disable the hardware
trigger support if touch screen is enabled.

This driver has been tested in AT91SAM9X5-EK and SAMA5D3x-EK.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
CC: devicetree@vger.kernel.org
Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      c8b11de0
  45. 17 10月, 2013 4 次提交
  47. 12 10月, 2013 1 次提交
  49. 10 10月, 2013 2 次提交