1. 02 7月, 2013 1 次提交
  2. 13 9月, 2012 2 次提交
    • J
      powerpc/fsl-pci: Unify pci/pcie initialization code · 905e75c4
      Jia Hongtao 提交于
      We unified the Freescale pci/pcie initialization by changing the fsl_pci
      to a platform driver. In previous PCI code architecture the initialization
      routine is called at board_setup_arch stage. Now the initialization is done
      in probe function which is architectural better. Also It's convenient for
      adding PM support for PCI controller in later patch.
      
      Now we registered pci controllers as platform devices. So we combine two
      initialization code as one platform driver.
      Signed-off-by: NJia Hongtao <B38951@freescale.com>
      Signed-off-by: NLi Yang <leoli@freescale.com>
      Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      905e75c4
    • T
      powerpc/85xx: Add support for P5040DS board · 4c30c143
      Timur Tabi 提交于
      Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
      is similar to the P5020DS.  Features of the P5040 are listed below, but
      not all of these features (e.g. DPAA networking) are currently supported.
      
      Four P5040 single-threaded e5500 cores built
          Up to 2.4 GHz with 64-bit ISA support
          Three levels of instruction: user, supervisor, hypervisor
      CoreNet platform cache (CPC)
          2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
      Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
       support Up to 1600MT/s
          Memory pre-fetch engine
      DPAA incorporating acceleration for the following functions
          Packet parsing, classification, and distribution (FMAN)
          Queue management for scheduling, packet sequencing and
      	congestion management (QMAN)
          Hardware buffer management for buffer allocation and
      	de-allocation (BMAN)
          Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes
          20 lanes at up to 5 Gbps
          Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
          Two 10 Gbps Ethernet MACs
          Ten 1 Gbps Ethernet MACs
      High-speed peripheral interfaces
          Two PCI Express 2.0/3.0 controllers
      Additional peripheral interfaces
          Two serial ATA (SATA 2.0) controllers
          Two high-speed USB 2.0 controllers with integrated PHY
          Enhanced secure digital host controller (SD/MMC/eMMC)
          Enhanced serial peripheral interface (eSPI)
          Two I2C controllers
          Four UARTs
          Integrated flash controller supporting NAND and NOR flash
      DMA
          Dual four channel
      Support for hardware virtualization and partitioning enforcement
          Extra privileged level for hypervisor support
      QorIQ Trust Architecture 1.1
          Secure boot, secure debug, tamper detection, volatile key storage
      Signed-off-by: NTimur Tabi <timur@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      4c30c143
  3. 29 3月, 2012 1 次提交
  4. 27 6月, 2011 3 次提交
  5. 14 10月, 2010 2 次提交
  6. 21 11月, 2009 1 次提交