Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

The touchscreen GPIO IRQ was used as a magic number. Define it properly in the
board header file. This is a simple cleanup patch.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

This patch adds support for the on-board IDE channel. I tested this with a CDROM
connected over 2.5-3.5 IDE reduction with external power supplied to the CDROM.
This was not tested with the Voipac 270-HDD-000 (official Voipac HDD module),
but I expect no problems.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

This adds support for the UCB1400 touchscreen found in the VPAC270 device.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

NOTE:
I wasn't able to get it running without reseting the HXOE (so it's there based
on my tests with the hardware). I'll have to investigate it properly when I have
more time.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Reviewed-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

PCMCIA support for Voipac PXA270
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

This patch adds basic support for the Voipac PXA270 SBC.
The device consists of the following hardware:
- PXA270 @ 520 MHz
- 256MB RAM (sparsemem, 2*128MB regions)
- 64MB NOR flash
- 640x480 LCD
- Ports: 2xUHC, 1xUDC, 1xPCMCIA, VGA, FFUART, 2xPS2, Speaker, MIC
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

This patch adds support for the Zipit Z2. The parts missing from this
patch are the battery support, SPI driver for the LCD and support for
the Silicon Serial ID chip.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

CM-X300 bootloader passes DRAM configuration information in ATAGS,
however, the first memory bank is reported at actual physical address 0x8000000.
Use the configuration information supplied by the bootloader and
cope with the necessity to have PHYS_ADDR=0xa0000000.
Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Tosa is now able to use generic matrix keypad driver instead of the deprecated
tosakbd.c, where CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES is still useful.  Move
it to mach/Kconfig.
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

REVISIT: change to GPIO18 is ugly, need to make sure whether that's
really necessary - GPIO18_RDY as an VLIO input signal - we don't
normally need to do such kind of trick during low power mode.
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Some pins are expected to keep their last level during suspend, and
introduce MFP_LPM_KEEP_OUTPUT for this.
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NJulia Lawall <julia@diku.dk>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

The assignments of res to the results of the two calls to
platform_get_resource make it impossible to use res in the error handling
code in the arguments to release_mem_region.

The semantic match that finds the former problem is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@r exists@
expression E, E1;
identifier f;
statement S1,S3;
iterator iter;
@@

if ((E == NULL && ...) || ...)
{
 ... when != false ((E == NULL && ...) || ...)
     when != true  ((E != NULL && ...) || ...)
     when != iter(E,...) S1
     when != E = E1
(
 sizeof(E->f)
|
* E->f
)
 ... when any
 return ...;
}
else S3
// </smpl>
Signed-off-by: NJulia Lawall <julia@diku.dk>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Configure both ssp and wm8753 in aspenite.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Support ssp devices in PXA168. PXA168 could reuse the code of PXA SSP.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Try to keep minimum ifdef in ssp.h.  Some of the definitions are valid
only to specific SoCs, and device drivers should be responsible to take
care of these difference.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

PXA_SSP is actually used by drivers like drivers/spi/pxa2xx_spi.c and
sound/soc/pxa/pxa-ssp.c, not by boards. Remove those incorrect 'select'
from Kconfig and make SOC_PXA_SSP to select.
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

No need to separate them as they should be together from the begining.
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

The previous definitions of SSCR0_SCR and SSCR0_SerClkDiv() prevented
them being used simultaneously when supporting multiple PXA SoCs, esp.
in drivers/spi/pxa2xx_spi.c, make them correct.

The change from SSCR0_SerClkDiv(2) to SSCR0_SCR(2), will make the result
a little bit different in pxa2xx_spi_probe(), however, since that's only
used as a default initialization value, it's acceptable.
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

The only use of corgi_ssp.c is corgi_ts.c, which is now deprecated
and removed. Remove corgi_ssp.c and corgi_lcd.c and their relevant
function declarations and data structures.
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Pavel Machek <pavel@ucw.cz>

This fixes a regression of

	7d58289f (mx1: prefix SOC specific defines with MX1_ and deprecate old names)
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>

Signed-off-by: NMichal Simek <monstr@monstr.eu>

1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP
2. Change BUG_ON to WARN_ON
3. Remove end aligned from CACHE_LOOP_LIMITS.
C implementation do not need aligned end address and ASM code do aligned
in their macros
4. ASM optimized  CACHE_RANGE_LOOP_1/2 macros needs to get aligned end address.
Because end address is compound from start + size, end address is the first address
which is exclude.

Here is the corresponding code which describe it.
+       int align = ~(line_length - 1);
+       end = ((end & align) == end) ? end - line_length : end & align;

a) end is aligned:
it is necessary to subtruct line length because we don't want to work with
next cacheline
b) end address is not aligned:
Just align it to be ready for ASM code.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

PCI_DMA_FROMDEVICE should call invalidation not flushing.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.

We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.

Here is the calculation for cacheline lenght 8  32bit=4Byte values
which is corresponding with SHIFT 5.
Signed-off-by: NMichal Simek <monstr@monstr.eu>