1. 21 10月, 2016 1 次提交
    • R
      clocksource: Add J-Core timer/clocksource driver · 9995f4f1
      Rich Felker 提交于
      At the hardware level, the J-Core PIT is integrated with the interrupt
      controller, but it is represented as its own device and has an
      independent programming interface. It provides a 12-bit countdown
      timer, which is not presently used, and a periodic timer. The interval
      length for the latter is programmable via a 32-bit throttle register
      whose units are determined by a bus-period register. The periodic
      timer is used to implement both periodic and oneshot clock event
      modes; in oneshot mode the interrupt handler simply disables the timer
      as soon as it fires.
      
      Despite its device tree node representing an interrupt for the PIT,
      the actual irq generated is programmable, not hard-wired. The driver
      is responsible for programming the PIT to generate the hardware irq
      number that the DT assigns to it.
      
      On SMP configurations, J-Core provides cpu-local instances of the PIT;
      no broadcast timer is needed. This driver supports the creation of the
      necessary per-cpu clock_event_device instances.
      
      A nanosecond-resolution clocksource is provided using the J-Core "RTC"
      registers, which give a 64-bit seconds count and 32-bit nanoseconds
      that wrap every second. The driver converts these to a full-range
      32-bit nanoseconds count.
      Signed-off-by: NRich Felker <dalias@libc.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: devicetree@vger.kernel.org
      Cc: linux-sh@vger.kernel.org
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Rob Herring <robh+dt@kernel.org>
      Link: http://lkml.kernel.org/r/b591ff12cc5ebf63d1edc98da26046f95a233814.1476393790.git.dalias@libc.orgSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      9995f4f1
  2. 30 9月, 2016 2 次提交
  3. 20 9月, 2016 12 次提交
  4. 14 9月, 2016 1 次提交
  5. 07 9月, 2016 12 次提交
  6. 06 9月, 2016 1 次提交
    • M
      ARM: 8611/1: l2x0: add PMU support · b828f960
      Mark Rutland 提交于
      The L2C-220 (AKA L220) and L2C-310 (AKA PL310) cache controllers feature
      a Performance Monitoring Unit (PMU), which can be useful for tuning
      and/or debugging. This hardware is always present and the relevant
      registers are accessible to non-secure accesses. Thus, no special
      firmware interface is necessary.
      
      This patch adds support for the PMU, plugging into the usual perf
      infrastructure. The overflow interrupt is not always available (e.g. on
      RealView PBX A9 it is not wired up at all), and the hardware counters
      saturate, so the driver does not make use of this. Instead, the driver
      periodically polls and reset counters as required to avoid losing
      events due to saturation.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NPawel Moll <pawel.moll@arm.com>
      Tested-by: NKim Phillips <kim.phillips@arm.com>
      Cc: Russell King <linux@armlinux.org.uk>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      b828f960
  7. 03 9月, 2016 2 次提交
  8. 01 9月, 2016 2 次提交
  9. 29 7月, 2016 1 次提交
  10. 23 7月, 2016 2 次提交
  11. 15 7月, 2016 4 次提交