1. 07 6月, 2015 1 次提交
  2. 19 4月, 2015 1 次提交
  3. 14 4月, 2015 1 次提交
    • L
      x86 msr-index: define MSR_TURBO_RATIO_LIMIT,1,2 · c4d30668
      Len Brown 提交于
      MSR_TURBO_RATIO_LIMIT has grown into a set of three registers.
      Add the documented names for them, in preparation
      for deleting the previous ad-hoc names:
      
      +#define MSR_TURBO_RATIO_LIMIT          0x000001ad
      +#define MSR_TURBO_RATIO_LIMIT1         0x000001ae
      +#define MSR_TURBO_RATIO_LIMIT2         0x000001af
      Signed-off-by: NLen Brown <len.brown@intel.com>
      Cc: x86@kernel.org
      c4d30668
  4. 02 4月, 2015 1 次提交
    • A
      perf/x86/intel/pt: Add Intel PT PMU driver · 52ca9ced
      Alexander Shishkin 提交于
      Add support for Intel Processor Trace (PT) to kernel's perf events.
      PT is an extension of Intel Architecture that collects information about
      software execuction such as control flow, execution modes and timings and
      formats it into highly compressed binary packets. Even being compressed,
      these packets are generated at hundreds of megabytes per second per core,
      which makes it impractical to decode them on the fly in the kernel.
      
      This driver exports trace data by through AUX space in the perf ring
      buffer, which is zero-copy mapped into userspace for faster data retrieval.
      Signed-off-by: NAlexander Shishkin <alexander.shishkin@linux.intel.com>
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Kaixu Xia <kaixu.xia@linaro.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Robert Richter <rric@kernel.org>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: acme@infradead.org
      Cc: adrian.hunter@intel.com
      Cc: kan.liang@intel.com
      Cc: markus.t.metzger@intel.com
      Cc: mathieu.poirier@linaro.org
      Link: http://lkml.kernel.org/r/1422614392-114498-1-git-send-email-alexander.shishkin@linux.intel.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      52ca9ced
  5. 10 2月, 2015 1 次提交
    • L
      tools/power turbostat: decode MSR_*_PERF_LIMIT_REASONS · 3a9a941d
      Len Brown 提交于
      The Processor generation code-named Haswell
      added MSR_{CORE | GFX | RING}_PERF_LIMIT_REASONS
      to explain when and how the processor limits frequency.
      
      turbostat -v
      will now decode these bits.
      
      Each MSR has an "Active" set of bits which describe
      current conditions, and a "Logged" set of bits,
      which describe what has happened since last cleared.
      
      Turbostat currently doesn't clear the log bits.
      Signed-off-by: NLen Brown <len.brown@intel.com>
      3a9a941d
  6. 09 1月, 2015 1 次提交
    • E
      KVM: nVMX: Improve nested msr switch checking · e9ac033e
      Eugene Korenevsky 提交于
      This patch improve checks required by Intel Software Developer Manual.
       - SMM MSRs are not allowed.
       - microcode MSRs are not allowed.
       - check x2apic MSRs only when LAPIC is in x2apic mode.
       - MSR switch areas must be aligned to 16 bytes.
       - address of first and last byte in MSR switch areas should not set any bits
         beyond the processor's physical-address width.
      
      Also it adds warning messages on failures during MSR switch. These messages
      are useful for people who debug their VMMs in nVMX.
      Signed-off-by: NEugene Korenevsky <ekorenevsky@gmail.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      e9ac033e
  7. 21 12月, 2014 1 次提交
  8. 03 12月, 2014 1 次提交
  9. 12 11月, 2014 2 次提交
  10. 16 8月, 2014 1 次提交
  11. 19 6月, 2014 1 次提交
  12. 30 5月, 2014 1 次提交
    • F
      x86/xsaves: Detect xsaves/xrstors feature · 6229ad27
      Fenghua Yu 提交于
      Detect the xsaveopt, xsavec, xgetbv, and xsaves features in processor extended
      state enumberation sub-leaf (eax=0x0d, ecx=1):
      Bit 00: XSAVEOPT is available
      Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set
      Bit 02: Supports XGETBV with ECX = 1 if set
      Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set
      
      The above features are defined in the new word 10 in cpu features.
      
      The IA32_XSS MSR (index DA0H) contains a state-component bitmap that specifies
      the state components that software has enabled xsaves and xrstors to manage.
      If the bit corresponding to a state component is clear in XCR0 | IA32_XSS,
      xsaves and xrstors will not operate on that state component, regardless of
      the value of the instruction mask.
      Signed-off-by: NFenghua Yu <fenghua.yu@intel.com>
      Link: http://lkml.kernel.org/r/1401387164-43416-3-git-send-email-fenghua.yu@intel.comSigned-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      6229ad27
  13. 09 5月, 2014 1 次提交
  14. 14 3月, 2014 2 次提交
  15. 24 2月, 2014 1 次提交
  16. 17 1月, 2014 1 次提交
  17. 15 1月, 2014 1 次提交
  18. 13 11月, 2013 1 次提交
    • L
      tools / power turbostat: Support Silvermont · 144b44b1
      Len Brown 提交于
      Support the next generation Intel Atom processor
      mirco-architecture, formerly called Silvermont.
      
      The server version, formerly called "Avoton",
      is named the "Intel(R) Atom(TM) Processor C2000 Product Family".
      
      The client version, formerly called "Bay Trail",
      is named the "Intel Atom Processor Z3000 Series",
      as well as various "Intel Pentium Processor"
      and "Intel Celeron Processor" brands, depending
      on form-factor.
      
      Silvermont has a set of MSRs not far off from NHM,
      but the RAPL register set is a sub-set of those previously supported.
      Signed-off-by: NLen Brown <len.brown@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      144b44b1
  19. 11 10月, 2013 1 次提交
  20. 26 6月, 2013 1 次提交
  21. 22 4月, 2013 1 次提交
  22. 21 4月, 2013 1 次提交
  23. 18 4月, 2013 1 次提交
  24. 01 4月, 2013 1 次提交
    • S
      perf/x86: Add memory profiling via PEBS Load Latency · f20093ee
      Stephane Eranian 提交于
      This patch adds support for memory profiling using the
      PEBS Load Latency facility.
      
      Load accesses are sampled by HW and the instruction
      address, data address, load latency, data source, tlb,
      locked information can be saved in the sampling buffer
      if using the PERF_SAMPLE_COST (for latency),
      PERF_SAMPLE_ADDR, PERF_SAMPLE_DATA_SRC types.
      
      To enable PEBS Load Latency, users have to use the
      model specific event:
      
       - on NHM/WSM: MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD
       - on SNB/IVB: MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD
      
      To make things easier, this patch also exports a generic
      alias via sysfs: mem-loads. It export the right event
      encoding based on the host CPU and can be used directly
      by the perf tool.
      
      Loosely based on Intel's Lin Ming patch posted on LKML
      in July 2011.
      Signed-off-by: NStephane Eranian <eranian@google.com>
      Cc: peterz@infradead.org
      Cc: ak@linux.intel.com
      Cc: acme@redhat.com
      Cc: jolsa@redhat.com
      Cc: namhyung.kim@lge.com
      Link: http://lkml.kernel.org/r/1359040242-8269-9-git-send-email-eranian@google.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      Signed-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      f20093ee
  25. 25 3月, 2013 1 次提交
  26. 16 2月, 2013 1 次提交
  27. 14 2月, 2013 1 次提交
    • L
      tools/power turbostat: display SMI count by default · 1ed51011
      Len Brown 提交于
      The SMI counter is popular -- so display it by default
      rather than requiring an option.  What the heck,
      we've blown the 80 column budget on many systems already...
      
      Note that the value displayed is the delta
      during the measurement interval.
      The absolute value of the counter can still be seen with
      the generic 32-bit MSR option, ie.  -m 0x34
      Signed-off-by: NLen Brown <len.brown@intel.com>
      1ed51011
  28. 09 2月, 2013 1 次提交
  29. 01 2月, 2013 1 次提交
  30. 15 12月, 2012 1 次提交
  31. 01 12月, 2012 1 次提交
    • W
      KVM: x86: Emulate IA32_TSC_ADJUST MSR · ba904635
      Will Auld 提交于
      CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
      
      Basic design is to emulate the MSR by allowing reads and writes to a guest
      vcpu specific location to store the value of the emulated MSR while adding
      the value to the vmcs tsc_offset. In this way the IA32_TSC_ADJUST value will
      be included in all reads to the TSC MSR whether through rdmsr or rdtsc. This
      is of course as long as the "use TSC counter offsetting" VM-execution control
      is enabled as well as the IA32_TSC_ADJUST control.
      
      However, because hardware will only return the TSC + IA32_TSC_ADJUST +
      vmsc tsc_offset for a guest process when it does and rdtsc (with the correct
      settings) the value of our virtualized IA32_TSC_ADJUST must be stored in one
      of these three locations. The argument against storing it in the actual MSR
      is performance. This is likely to be seldom used while the save/restore is
      required on every transition. IA32_TSC_ADJUST was created as a way to solve
      some issues with writing TSC itself so that is not an option either.
      
      The remaining option, defined above as our solution has the problem of
      returning incorrect vmcs tsc_offset values (unless we intercept and fix, not
      done here) as mentioned above. However, more problematic is that storing the
      data in vmcs tsc_offset will have a different semantic effect on the system
      than does using the actual MSR. This is illustrated in the following example:
      
      The hypervisor set the IA32_TSC_ADJUST, then the guest sets it and a guest
      process performs a rdtsc. In this case the guest process will get
      TSC + IA32_TSC_ADJUST_hyperviser + vmsc tsc_offset including
      IA32_TSC_ADJUST_guest. While the total system semantics changed the semantics
      as seen by the guest do not and hence this will not cause a problem.
      Signed-off-by: NWill Auld <will.auld@intel.com>
      Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>
      ba904635
  32. 24 11月, 2012 2 次提交
  33. 02 11月, 2012 1 次提交
  34. 04 10月, 2012 1 次提交
  35. 10 9月, 2012 2 次提交
  36. 08 3月, 2012 1 次提交