- 01 3月, 2010 3 次提交
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由 Robert Richter 提交于
For consistency reasons this patch renames ARCH_PERFMON_EVENTSEL0_ENABLE to ARCH_PERFMON_EVENTSEL_ENABLE. The following is performed: $ sed -i -e s/ARCH_PERFMON_EVENTSEL0_ENABLE/ARCH_PERFMON_EVENTSEL_ENABLE/g \ arch/x86/include/asm/perf_event.h arch/x86/kernel/cpu/perf_event.c \ arch/x86/kernel/cpu/perf_event_p6.c \ arch/x86/kernel/cpu/perfctr-watchdog.c \ arch/x86/oprofile/op_model_amd.c arch/x86/oprofile/op_model_ppro.c Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Robert Richter 提交于
Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Robert Richter 提交于
This patch moves code from oprofile to perf_event.h to make it also available for usage by perf. Signed-off-by: NRobert Richter <robert.richter@amd.com>
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- 28 2月, 2010 1 次提交
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由 Frederic Weisbecker 提交于
Remove the name field from the arch_hw_breakpoint. We never deal with target symbols in the arch level, neither do we need to ever store it. It's a legacy for the previous version of the x86 breakpoint backend. Let's remove it. Signed-off-by: NFrederic Weisbecker <fweisbec@gmail.com> Cc: K.Prasad <prasad@linux.vnet.ibm.com> Cc: Linus Torvalds <torvalds@linux-foundation.org>
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- 27 2月, 2010 1 次提交
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由 Peter Zijlstra 提交于
Avoid kernels from exploding on AMD machines when they have any lock debugging bits enabled. Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 26 2月, 2010 17 次提交
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由 Peter Zijlstra 提交于
Split amd,p6,intel into separate files so that we can easily deal with CONFIG_CPU_SUP_* things, needed to make things build now that perf_event.c relies on symbols from amd.c Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <new-submission> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Robert Richter 提交于
During switching virtual counters there is access to perfctr msrs. If the counter is not available this fails due to an invalid address. This patch fixes this. Cc: stable@kernel.org Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Robert Richter 提交于
Cc: stable@kernel.org Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Robert Richter 提交于
Multiple virtual counters share one physical counter. The reservation of virtual counters fails due to duplicate allocation of the same counter. The counters are already reserved. Thus, virtual counter reservation may removed at all. This also makes the code easier. Cc: stable@kernel.org Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Naga Chumbalkar 提交于
Currently, oprofile fails silently on platforms where a non-OS entity such as the system firmware "enables" and uses a performance counter. There is a warning in the code for this case. The warning indicates an already running counter. If oprofile doesn't collect data, then try using a different performance counter on your platform to monitor the desired event. Delete the counter from the desired event by editing the /usr/share/oprofile/<cpu_type>/<cpu>/events file. If the event cannot be monitored by any other counter, contact your hardware or BIOS vendor. Cc: Shashi Belur <shashi-kiran.belur@hp.com> Cc: Tony Jones <tonyj@suse.de> Signed-off-by: NNaga Chumbalkar <nagananda.chumbalkar@hp.com> Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Robert Richter 提交于
This patch generates a warning if a counter is already active. Implemented for AMD and P6 models. P4 is not supported. Cc: Naga Chumbalkar <nagananda.chumbalkar@hp.com> Cc: Shashi Belur <shashi-kiran.belur@hp.com> Cc: Tony Jones <tonyj@suse.de> Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Robert Richter 提交于
IBS selects an op (execution operation) for sampling by counting either cycles or dispatched ops. Better statistical samples can be produced by adding a software generated random offset to the periodic op counter value with each sample. This patch adds software randomization to the IBS periodic op counter. The lower 12 bits of the 20 bit counter are randomized. IbsOpCurCnt is initialized with a 12 bit random value. There is a work around if the hw can not write to IbsOpCurCnt. Then the lower 8 bits of the 16 bit IbsOpMaxCnt [15:0] value are randomized in the range of -128 to +127 by adding/subtracting an offset to the maximum count (IbsOpMaxCnt). The linear feedback shift register (LFSR) algorithm is used for pseudo-random number generation to have low impact to the memory system. Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Suravee Suthikulpanit 提交于
This patch implements a linear feedback shift register (LFSR) for pseudo-random number generation for IBS. For IBS measurements it would be good to minimize memory traffic in the interrupt handler since every access pollutes the data caches. Computing a maximal period LFSR just needs shifts and ORs. The LFSR method is good enough to randomize the ops at low overhead. 16 pseudo-random bits are enough for the implementation and it doesn't matter that the pattern repeats with a fairly short cycle. It only needs to break up (hard) periodic sampling behavior. The logic was designed by Paul Drongowski. Signed-off-by: NSuravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Robert Richter 提交于
This patch adds IBS feature detection using cpuid flags. An IBS capability mask is introduced to test for certain IBS features. The bit mask is the same as for IBS cpuid feature flags (Fn8000_001B_EAX), but bit 0 is used to indicate the existence of IBS. The patch also changes the handling of the IbsOpCntCtl bit (periodic op counter count control). The oprofilefs file for this feature (ibs_op/dispatched_ops) will be only exposed if the feature is available, also the default for the bit is set to count clock cycles. In general, the userland can detect the availability of a feature by checking for the corresponding file in oprofilefs. If it exists, the feature also exists. This may lead to a dynamic file layout depending on the cpu type with that the userland has to deal with. Current opcontrol is compatible. Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Robert Richter 提交于
Standard AMD systems have the same number of nodes as there are northbridge devices. However, there may kernel configurations (especially for 32 bit) or system setups exist, where the node number is different or it can not be detected properly. Thus the check is not reliable and may fail though IBS setup was fine. For this reason it is better to remove the check. Cc: stable <stable@kernel.org> Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Robert Richter 提交于
OProfile support for IBS is now for several versions in the kernel. The feature is stable now and the code can be activated permanently. As a side effect IBS now works also on nosmp configs. Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Robert Richter 提交于
OProfile is already used for a long time and no longer experimental. Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Robert Richter 提交于
The commit 1155de47 ring-buffer: Make it generally available already made ring-buffer available without the TRACING option enabled. This patch removes the TRACING dependency from oprofile. Fixes also oprofile configuration on ia64. The patch also applies to the 2.6.32-stable kernel. Reported-by: NTony Jones <tonyj@suse.de> Cc: stable@kernel.org Signed-off-by: NRobert Richter <robert.richter@amd.com>
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由 Peter Zijlstra 提交于
We re-program the event control register every time we reset the count, this appears to be superflous, hence remove it. Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl> Cc: Arjan van de Ven <arjan@linux.intel.com> LKML-Reference: <new-submission> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Peter Zijlstra 提交于
Since the cpu argument to hw_perf_group_sched_in() is always smp_processor_id(), simplify the code a little by removing this argument and using the current cpu where needed. Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl> Cc: David Miller <davem@davemloft.net> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> LKML-Reference: <1265890918.5396.3.camel@laptop> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Stephane Eranian 提交于
This patch adds correct AMD NorthBridge event scheduling. NB events are events measuring L3 cache, Hypertransport traffic. They are identified by an event code >= 0xe0. They measure events on the Northbride which is shared by all cores on a package. NB events are counted on a shared set of counters. When a NB event is programmed in a counter, the data actually comes from a shared counter. Thus, access to those counters needs to be synchronized. We implement the synchronization such that no two cores can be measuring NB events using the same counters. Thus, we maintain a per-NB allocation table. The available slot is propagated using the event_constraint structure. Signed-off-by: NStephane Eranian <eranian@google.com> Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <4b703957.0702d00a.6bf2.7b7d@mx.google.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Stephane Eranian 提交于
In certain situations, the kernel may need to stop and start the same event rapidly. The current PMU callbacks do not distinguish between stop and release (i.e., stop + free the resource). Thus, a counter may be released, then it will be immediately re-acquired. Event scheduling will again take place with no guarantee to assign the same counter. On some processors, this may event yield to failure to assign the event back due to competion between cores. This patch is adding a new pair of callback to stop and restart a counter without actually release the underlying counter resource. On stop, the counter is stopped, its values saved and that's it. On start, the value is reloaded and counter is restarted (on x86, actual restart is delayed until perf_enable()). Signed-off-by: NStephane Eranian <eranian@google.com> [ added fallback to ->enable/->disable for all other PMUs fixed x86_pmu_start() to call x86_pmu.enable() merged __x86_pmu_disable into x86_pmu_stop() ] Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <4b703875.0a04d00a.7896.ffffb824@mx.google.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 25 2月, 2010 1 次提交
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由 Carlos O'Donell 提交于
Set the PCI CLS early in the boot process to prevent device failures. In pcibios_set_master use the new pci_cache_line_size instead of a hard-coded value. Signed-off-by: NCarlos O'Donell <carlos@codesourcery.com> Reviewed-by: NGrant Grundler <grundler@google.com> Signed-off-by: NKyle McMartin <kyle@redhat.com>
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- 24 2月, 2010 3 次提交
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由 Steven J. Magnani 提交于
Trailing semicolon causes compilation involving out_le32() to fail. Signed-off-by: NSteven J. Magnani <steve@digidescorp.com> Signed-off-by: NMichal Simek <monstr@monstr.eu>
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由 Michal Simek 提交于
I create wrong asm code but none test shows that this part of code is wrong. I am not convinces that were good idea to create asm optimized macros for caches. The reason is that there is not optimization with previous code that's why make sense to add old code and do some benchmarking which functions are faster. Signed-off-by: NMichal Simek <monstr@monstr.eu>
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由 Hedi Berriche 提交于
Revert the change made to arch/ia64/sn/kernel/setup.c by commit 204fba4a as it breaks the build. Fixing the build the b94b0808 way breaks xpc because genksyms then fails to generate an CRC for per_cpu____sn_cnodeid_to_nasid because of limitations in the generic genksyms code. Signed-off-by: NHedi Berriche <hedi@sgi.com> Signed-off-by: NTony Luck <tony.luck@intel.com>
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- 23 2月, 2010 3 次提交
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由 Hauke Mehrtens 提交于
Ignoring the last page when ddr size is 128M. Cached accesses to last page is causing the processor to prefetch using address above 128M stepping out of the DDR address space. Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/981/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Yoichi Yuasa 提交于
arch/mips/mm/highmem.c: In function 'kmap_init': arch/mips/mm/highmem.c:130: error: 'init_mm' undeclared (first use in this function) arch/mips/mm/highmem.c:130: error: (Each undeclared identifier is reported only once arch/mips/mm/highmem.c:130: error: for each function it appears in.) Signed-off-by: NYoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/980/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Roland McGrath 提交于
This reverts commit 81bf550d. HAVE_ARCH_TRACEHOOK requires defining the user_regset interfaces, including task_user_regset_view(). parisc doesn't do that yet, so don't lie about it. Signed-off-by: NRoland McGrath <roland@redhat.com>
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- 22 2月, 2010 1 次提交
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由 David S. Miller 提交于
Commit 085219f7 ("sparc32: use proper types in struct stat") Accidently changed the struct stat uid/gid members to uid_t and gid_t, but those get set to __kernel_uid32_t and __kernel_gid32_t respectively. Those are of type 'int' but the structure is meant to have 'short'. So use uid16_t and gid16_t to correct this. Reported-by: NRob Landley <rob@landley.net> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 21 2月, 2010 1 次提交
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由 Russell King 提交于
Some glibc versions intentionally create lots of alignment faults in their gconv code, which if not fixed up, results in segfaults during boot. This can prevent systems booting properly. There is no clear hard-configurable default for this; the desired default depends on the nature of the userspace which is going to be booted. So, provide a way for the alignment fault handler to be configured via the kernel command line. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 20 2月, 2010 5 次提交
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由 Russell King 提交于
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Abdoulaye Walsimou Gaye 提交于
This patch fix the below build error for arm1026ej-s processor (IntegratorCP/arm1026ej-s board). CC init/main.o In file included from include/linux/highmem.h:8, from include/linux/pagemap.h:10, from include/linux/mempolicy.h:62, from init/main.c:52: arch/arm/include/asm/cacheflush.h:134:2: error: #error Unknown cache maintainence model make[1]: *** [init/main.o] Erreur 1 make: *** [init] Erreur 2 Signed-off-by: NAbdoulaye Walsimou Gaye <walsimou@walsimou.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 David S. Miller 提交于
Thanks to testcase and report from Brad Spengler: -------------------- #include <stdio.h> typedef int (* _wee)(void); int main(void) { char buf[8] = { '\x81', '\xc7', '\xe0', '\x08', '\x81', '\xe8', '\x00', '\x00' }; _wee wee; printf("%p\n", &buf); wee = (_wee)&buf; wee(); return 0; } -------------------- TSB I-tlb load code tries to use andcc to check the _PAGE_EXEC_4U bit, but that's bit 12 so it gets sign extended all the way up to bit 63 and the test nearly always passes as a result. Use sethi to fix the bug. Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Frederic Weisbecker 提交于
When the user enables breakpoints through dr7, he can choose between "local" or "global" enable bits but given how linux is implemented, both have the same effect. That said we don't keep track how the user enabled the breakpoints so when the user requests the dr7 value, we only translate the "enabled" status using the global enabled bits. It means that if the user enabled a breakpoint using the local enabled bit, reading back dr7 will set the global bit and clear the local one. Apps like Wine expect a full dr7 POKEUSER/PEEKUSER match for emulated softwares that implement old reverse engineering protection schemes. We fix that by keeping track of the whole dr7 value given by the user in the thread structure to drop this bug. We'll think about something more proper later. This fixes a 2.6.32 - 2.6.33-x ptrace regression. Reported-and-tested-by: NMichael Stefaniuc <mstefani@redhat.com> Signed-off-by: NFrederic Weisbecker <fweisbec@gmail.com> Acked-by: NK.Prasad <prasad@linux.vnet.ibm.com> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Maneesh Soni <maneesh@linux.vnet.ibm.com> Cc: Alexandre Julliard <julliard@winehq.org> Cc: Rafael J. Wysocki <rjw@sisk.pl> Cc: Maciej Rutecki <maciej.rutecki@gmail.com>
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由 Frederic Weisbecker 提交于
Before we had a generic breakpoint API, ptrace was accepting breakpoints on NULL address in x86. The new API refuse them, without given strong reasons. We need to follow the previous behaviour as some userspace apps like Wine need such NULL breakpoints to ensure old emulated software protections are still working. This fixes a 2.6.32 - 2.6.33-x ptrace regression. Reported-and-tested-by: NMichael Stefaniuc <mstefani@redhat.com> Signed-off-by: NFrederic Weisbecker <fweisbec@gmail.com> Acked-by: NK.Prasad <prasad@linux.vnet.ibm.com> Acked-by: NRoland McGrath <roland@redhat.com> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Maneesh Soni <maneesh@linux.vnet.ibm.com> Cc: Alexandre Julliard <julliard@winehq.org> Cc: Rafael J. Wysocki <rjw@sisk.pl> Cc: Maciej Rutecki <maciej.rutecki@gmail.com>
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- 19 2月, 2010 2 次提交
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由 Roel Kluin 提交于
It appears the wrong GPIO registers were used Signed-off-by: NRoel Kluin <roel.kluin@gmail.com> Signed-off-by: NPaulius Zaleckas <paulius.zaleckas@gmail.com>
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由 Santosh Shilimkar 提交于
The 'outer_cache' variable is needed by the outer_inv_range(), outer_clean_range() and outer_flush_range() functions, which are declared as inline in asm/cacheflush.h. Otherwise drivers built as a loadable module, which access these functions, will have an undefined symbol. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 18 2月, 2010 2 次提交
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由 Len Brown 提交于
We broke "acpi=ht" in 2.6.32 by disabling MADT parsing for acpi=disabled. e5b8fc6a This also broke systems which invoked acpi=ht via DMI blacklist. acpi=ht is a really ugly hack, but restore it for those that still use it. http://bugzilla.kernel.org/show_bug.cgi?id=14886Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Kristoffer Glembo 提交于
Use type instead of name in comparison. Signed-off-by: NKristoffer Glembo <kristoffer@gaisler.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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