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  1. 21 8月, 2009 1 次提交
  3. 15 8月, 2009 6 次提交
  5. 04 8月, 2009 2 次提交
  7. 22 7月, 2009 1 次提交
    • P
      sh: Migrate from PG_mapped to PG_dcache_dirty. · 2277ab4a
      由 Paul Mundt 提交于 
      This inverts the delayed dcache flush a bit to be more in line with other
platforms. At the same time this also gives us the ability to do some
more optimizations and cleanup. Now that the update_mmu_cache() callsite
only tests for the bit, the implementation can gradually be split out and
made generic, rather than relying on special implementations for each of
the peculiar CPU types.

SH7705 in 32kB mode and SH-4 still need slightly different handling, but
this is something that can remain isolated in the varying page copy/clear
routines. On top of that, SH-X3 is dcache coherent, so there is no need
to bother with any of these tests in the PTEAEX version of
update_mmu_cache(), so we kill that off too.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      2277ab4a
  9. 20 7月, 2009 1 次提交
  11. 04 7月, 2009 1 次提交
    • M
      sh: hwblk for sh7722 · a61c1a63
      由 Magnus Damm 提交于 
      This patch contains the sh7722 specific hwblk implementation.

Hwblk ids are added to the processor specific header file,
module stop bits and areas are kept track of as hwblks,
clocks are converted to make use of the shared hwblk code.
Code to determine allowed sleep modes is also added.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      a61c1a63
  13. 11 6月, 2009 4 次提交
  15. 02 6月, 2009 1 次提交
  17. 01 6月, 2009 1 次提交
  19. 12 5月, 2009 1 次提交
    • M
      sh: remove old TMU driver · f19900b2
      由 Magnus Damm 提交于 
      This patch removes the old TMU driver (CONFIG_SH_TMU/timer-tmu.c)

As replacement, select the sh_tmu driver with CONFIG_SH_TIMER_TMU
and configure timer channel using platform data.

If multiple TMU channels are enabled using platform data, use the
earlytimer parameter on the kernel command line to select channel.
For instance, use "earlytimer=sh_tmu.0" to select the first channel.

To verify which timer is being used, look at printouts or the timer
irq count in /proc/interrupts.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      f19900b2
  21. 16 4月, 2009 1 次提交
  23. 31 3月, 2009 1 次提交
  25. 17 3月, 2009 1 次提交
    • P
      sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores. · 8263a67e
      由 Paul Mundt 提交于 
      This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores
that implement the PTAEX register and respective functionality. Presently
only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs).

The main change is in how the PTE is written out when loading the entry
in to the TLB, as well as in how the TLB entry is selectively flushed.

While SH-X2 extended mode splits out the memory-mapped U and I-TLB data
arrays for extra bits, extended ASID mode splits out the address arrays.
While we don't use the memory-mapped data array access, the address
array accesses are necessary for selective TLB flushes, so these are
implemented newly and replace the generic SH-4 implementation.

With this, TLB flushes in switch_mm() are almost non-existent on newer
parts.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      8263a67e
  27. 10 3月, 2009 1 次提交
  29. 03 3月, 2009 1 次提交
  31. 28 10月, 2008 1 次提交
  33. 23 10月, 2008 1 次提交
  35. 20 10月, 2008 1 次提交
  37. 29 7月, 2008 1 次提交