If max77686 chip is instantiated from device tree, it is desirable to
have an OF clock provider to allow device tree based look-up of clocks.
This patch adds OF clock provider registration to the clk-max77686
driver.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

As a prerequisite for further patch adding OF clock provider support to
the driver, this patch changes the driver to store an array of struct
clk * as driver data.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch fixes invalid kfree() and adds missing call to clk_unregister()
in error and remove paths in max77686_clk_probe(). While at it, error
handling is also cleaned up.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

As a preparation for further patches, this patch modifies the clock
registration helper function to return a pointer to the newly registered
clock. No functional change is done to the driver.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The function can simply return 0, without jumping to a separate label,
which does exactly the same. This patch does not introduce any
functional change, just a clean-up.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

It is usually nice to know frequency of a clock, so this patch adds a
.recalc_rate() callback returning rates of provided clocks.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Changing status of clock gates in max77686 requires i2c transfers, which
can sleep, so this is done in prepare and unprepare callbacks. Due to
this, checking whether whether the clock is ungated must be done
in is_prepared() callback as well, for consistency.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0.  Add a clock ID for it so that
we can reference it in device trees.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings.  Default names will be used
when an input clock is not given.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The Exynos AudioSS clock controller will later be modified to allow
input clocks to be specified via device-tree in order to support
multiple Exynos SoCs.  This will introduce a dependency on the core
SoC clock controller being initialized first so that the AudioSS driver
can look up its input clocks, but the order in which clock providers
are probed in of_clk_init() is not guaranteed.  Since deferred probing
is not supported in of_clk_init() and the AudioSS block is not the core
controller, we can initialize it later as a platform device.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Register the APLL rate table so that we can set the APLL rate from
the cpufreq driver.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the
clock rate in the cpufreq driver.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds mout_aclk333_sub mux clock and updates gate clocks from
MFC domain to have it as their parent as specified in SoC documentation.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

According to SoC documentation, input 5 of mout_audio muxes is connected
to xxti (named fin_pll in the driver). This patch corrects defined
parent arrays to match SoC documentation.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

This patch updates mux parent arrays with unpopulated mux inputs, as all
inputs need to be specified in parent arrays passed to
clk_register_mux(), otherwise clk_set_parent() can generate out of bound
accesses to the array.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions
of GSCL domain gate clocks to use it as their parent, as specified in
SoC documentation.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

This patch renames all mux clocks to start with mout_ prefix and all div
clocks to start with div_ prefix for consistency with other clocks
already defined this way.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

This patch reorders clock definitions, so they are sorted by register
addresses and bitfield shifts. When at it, blank lines are added to
separate definitions of clocks from different registers.

Overall this should make the driver more readable and reduce the number
of potential conflicts when adding new entries.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

Move reg_save[] into CONFIG_PM_SLEEP dependency block as it is used only
by suspend and resume functions.

This fixes the warning on CONFIG_PM_SLEEP=n:
drivers/clk/samsung/clk-exynos-audss.c:29:22: warning: ‘reg_save’ defined but not used [-Wunused-variable]
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused
clock at boot-up. This can lead to failures in operation of above blocks,
because they can not be configured properly if this clock is disabled.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The CLK_GATE_IP_ACP register offset is incorrectly listed making
definition of g2d clock incorrect, which may lead to system failures
when trying to use G2D on systems on which firmware gates this clock
by default. Fix this and the register ordering as well.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The gate clocks for the MFC sysmmus appear to be flipped, i.e.
GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
Fix this so that the MFC will start up.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The SRC_MFC register offset was incorrect, which could cause have caused
wrong calculation of rate of sclk_mfc clock, that could in turn lead to
incorrect operation of MFC. This patch corrects it.
Signed-off-by: NSeung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NEmilio López <emilio@elopez.com.ar>

The DT nodes should look like

    abc_clk: clk@deadbeef {
        ...
        clock-output-names = "abc";
    }

But our old DT nodes look like

    abc: abc@deadbeef {
        ...
    }

So, let's support both formats, until we can transition everything
to the new, correct one.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMike Turquette <mturquette@linaro.org>

This commit implements support for the "module 0" type of clocks, as
used by MMC, IR, NAND, SATA and other components.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMike Turquette <mturquette@linaro.org>

This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMike Turquette <mturquette@linaro.org>

We will be needing this to register a factor clock as parent with leaf
divisors on a single call.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMike Turquette <mturquette@linaro.org>

This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NMike Turquette <mturquette@linaro.org>

This was pointed out during the review of the factor patches. Let's
indicate what does that magic 5 mean.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMike Turquette <mturquette@linaro.org>

This commit reworks factors clock registration to be done behind a
composite clock. This allows us to additionally add a gate, mux or
divisors, as it will be needed by some future PLLs.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NMike Turquette <mturquette@linaro.org>

Populate ${DEBUGS_MOUNT_POINT}/clk if CONFIG_DEBUG_FS is set. This
eliminates the extra (annoying) step of enabling the config option
manually.
Signed-off-by: NMike Turquette <mturquette@linaro.org>

'break' after 'goto' is redundant. Remove it.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NJonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>