the default tx/rx chainmask for AR9462 is 0x3.
this patch helps to assign 0x3 rather than 0x7 for
AR9462 with the help of fix_chainmask module if something
goes wrong in reading tx/rx chain mask from OTP/EEPROM
card(though its very unlikely)
Signed-off-by: NMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

only for AR9485 (or) later chipsets TxIQ calibration
runs as part of AGC calibration. without this patch
TX IQ cal completion i.e. ar9003_hw_tx_iq_cal_run won't be executed
for AR9003
Reviewed-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Cc: Wilson Tsao <wtsao@qca.qualcomm.com>
Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

here we check for BT state and if BT calibration has started,
give 25ms for BT Calibration to finish. we also take care of 2G/5G
switch and LNA transfer incase WLAN is operating in 5G. in case the BT
state is awake when we do WLAN calibration re-calibrate and we reset
the message exchange between WLAN and BT. BT is given preference when
simultaneous CAL request happens. calibration for WLAN/BT is done
assuming that the other co-existing module is in awake state, if not
we continue to do calibration while if the other module's state changes
we need to do restart the calibration handshake

Cc: Wilson Tsao <wtsao@qca.qualcomm.com>
Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Cc: Wilson Tsao <wtsao@qca.qualcomm.com>
Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

send halt BT GPM if the chip is in network sleep and BT state
is awake

Cc: Wilson Tsao <wtsao@qca.qualcomm.com>
Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

AR9462 chips have the capabilities to provoide bluetooth
profile information. For non-AR9462 btcoex chips, the BT
priority traffic was identified by periodically polling
the respective registers and updated dutycycle, stomptype,
etc. As AR9462 chip offers the BT profile informations,
let us make use of that to update aggregation limit,
dutycycle, stomptype and wieghtages.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

The code here treats very large values of "limit" as less than
MAX_POWER_RATE because of the cast to int.  We should do the compare
as u32 instead.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: NPavel Roskin <proski@gnu.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

During the fast channel change noise floor values are being loaded
twice at init_cal and after channel_change. The commit "ath9k_hw:
Improve fast channel change for AR9003 chips" overlooked it that
caused failure to load nf while doing bgscan. This patch performs noise
floor calibration after the fast and full reset.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

The device.h header was including module.h, making it present for
most of these drivers.  But we want to clean that up.  Call out the
include of module.h in the modular network drivers.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

Renamed to be in sync with Marketing term and to avoid
confusion with other chip names.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Support the fast channel change across band switch only when there
are available of reusable cabliration results. And also observed that
doing agc control calibration on fastcc, sometimes causing calibration
timeout. Hence changing agc control to be run only on full chip reset.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Supported calibrations of radio retention table (RTT) are
	- DC offset
	- Filter
	- Peak detect
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

The commit "ath9k_hw: Improve fast channel change for AR9003 chips"
fixes the fast channel change issue for AR9003 chips that was
originally observed in AR9382 chip. Hence enabling fastcc support
again for 11A channel for AR9003 chips.

Cc: Paul Stewart <pstew@google.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Currently Tx IQ calibration is enabled by default for all AR9003
chips. But for AR9480, the calibration status should be read from
chip after processing ini. And also the carrier leak calibration
status is checked during init cal. As the init_cal is being called
for fast channel change too, the tx_cl status only be read after
full reset. Hence moving that into process ini function.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

This patch adds support to reuse Carrier leak calibration
during fast channel change for AR9480 chips.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

In order to reduce the overall scan time, fast channel change
should be implemented properly. This patch adds fast channel
change support across band switch or channel mode switch
instead of doing full chip reset. During the fastcc, tx iqcal
measurements are preserved and will be reloaded after successful
the channel change.

This patch also addressed fast channel issue where the STA can not
see APs in higher than operating channel on 5GHz band after
the association.

Cc: Paul Stewart <pstew@google.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Because of not clearing Bit 14 of AR_WA, the ASPM L1 is not
enabled when entering into sleep mode. AR9480 does not need
bit 14 to be set.

Cc: stable@kernel.org
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

It is unused since the previous dead code that was using it had been
removed earlier.
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

The code for handling various restrictions concerning regulatory limits,
antenna gain, etc. is very convoluted and duplicated across various
EEPROM parsing implementations, making it hard to review.

This patch partially cleans up the mess by unifying regulatory limit
handling in one function and simplifying handling of antenna gain.
It also removes unused transmit power scaling arrays from the EEPROM code,
which belonged to an unimplemented API that isn't supposed to be in
the driver anyway.
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

the AR_SREV register does not seems to indicate whether AR9480 is
pci_express capable or not though the other information like macVersion
etc can be obtained properly. this fix is essential as ASPM won't be intialized
and its related driver functionality ath9k_hw_configpcipowersave won't be
called
Signed-off-by: NMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

this patch fixes the assumption of maximum number of GPIO pins present
in AR9287/AR9300. this fix is essential as we might encounter some
functionality issues involved in accessing the status of GPIO pins which
are all incorrectly assumed to be not within the range of max_num_gpio
of AR9300/AR9287 chipsets

Cc: stable@kernel.org
Signed-off-by: NMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

AR9003 seems to have issues sometimes with fast channel change
in 5GHz and this case is handled specifically for AR9280 by doing
a full reset. Let's do a full reset for 5GHz channles of AR9380
& for all channels of AR9280 pci chips.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

This patch adds support for AR946/8x chipets.
Signed-off-by: NSenthil Balasubramanian <senthilb@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

we already have ah->{rx,tx}chainmask for the same purpose
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

In commit 9c204b46
(ath9k_hw: do not limit initial tx power to 20 dbm),
setting of txpower was broken.

This patch fixes it by initializing reg_pwr from the new
power limit, not the previous value.
Signed-off-by: NBill Jordan <bjordan@rajant.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Rx latecy to start signal(usec) of 11a is 41 not 37 and
also corrected the rx delay in quarter rate.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

It is only used to workaround interoperability issues related to longer
delays in receiving the block ack, so it is not necessary to apply it
to the CTS exchange.
Should improve throughput slightly, especially when there are lots
of retransmissions.
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

For AR9287 v1.3+ chips, MAC runs at 117MHz. But the initvals
IFS parameters are loaded based on 44/88MHz clockrate. So
eifs/usec from ini should not be used for AR9287 v1.3+.
The mentioned values are tested on 2 chain HT40 mode.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Initialize 9us slot time as that is what is used mostly
(for non-ERP cases) and also to be in sync with initvals.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

AR9340 is not listed in ath_mac_bb_names, which leads to such a message:
ieee80211 phy0: Atheros AR???? Rev:0 mem=0xb8100000, irq=2
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Here are the AR9580 1.0 initvals checksums using the
Atheros initvals-tools [1]. This is useful for when
we udate the initvals again with other values. It ensures
that we match the same initvals used internally. The
tool is documented on the wiki [2].

$ ./initvals -f ar9580-1p0
0x00000000e912711f        ar9580_1p0_modes_fast_clock
0x000000004a488fc7        ar9580_1p0_radio_postamble
0x00000000f3888b02        ar9580_1p0_baseband_core
0x0000000003f783bb        ar9580_1p0_mac_postamble
0x0000000094be244a        ar9580_1p0_low_ob_db_tx_gain_table
0x0000000094be244a        ar9580_1p0_high_power_tx_gain_table
0x0000000090be244a        ar9580_1p0_lowest_ob_db_tx_gain_table
0x00000000ed9eaac6        ar9580_1p0_baseband_core_txfir_coeff_japan_2484
0x00000000c4d66d1b        ar9580_1p0_mac_core
0x00000000e8e9043a        ar9580_1p0_mixed_ob_db_tx_gain_table
0x000000003521a300        ar9580_1p0_wo_xlna_rx_gain_table
0x00000000301fc841        ar9580_1p0_soc_postamble
0x00000000a9a06b3a        ar9580_1p0_high_ob_db_tx_gain_table
0x00000000a15ccf1b        ar9580_1p0_soc_preamble
0x0000000029495000        ar9580_1p0_rx_gain_table
0x0000000037ac0ee8        ar9580_1p0_radio_core
0x00000000603a1b80        ar9580_1p0_baseband_postamble
0x000000003d8b4396        ar9580_1p0_pcie_phy_clkreq_enable_L1
0x00000000398b4396        ar9580_1p0_pcie_phy_clkreq_disable_L1
0x00000000397b4396        ar9580_1p0_pcie_phy_pll_on_clkreq

[1] git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/initvals-tool.git
[2] http://wireless.kernel.org/en/users/Drivers/ath9k_hw/initvals-tool

Cc: David Quan <dquan@qca.qualcomm.com>
Cc: Kathy Giori <kgiori@qca.qualcomm.com>
Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Tested-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NLuis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

The EIFS value read from AR_D_GBL_IFS_EIFS register in core clocks and then
written back as microsecond value.
Signed-off-by: NAlex Hacker <hacker@epn.ru>
Acked-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Disable ASPM in pci ->probe on upstream (device) and downstream
(PCIe port) component. According to e1000e driver authors this is
required. I did not find that requirement in PCIe spec, but it seems
to be logical for me.

This need to be fixed for CONFIG_PCIEASPM, that will be done later ...
Signed-off-by: NStanislaw Gruszka <sgruszka@redhat.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Currently ath9k presents the internal calibrated noise floor as channel
noise measurement, however this results in highly chip specific values
that are only useful as relative measurements but do not resemble any
real channel noise values.

In order to give a much better approximation of the real channel noise,
add the difference between the measured noise floor and the nominal
chip specific noise floor to the default minimum channel noise value,
which is currently used to calculate the signal strength from the RSSI
value. This may not be 100% accurate, but it's much better than what's
there before.
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

When testing for tx power, bypass the default limits.
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

We receive many bug reports about system hang during suspend/resume
when ath9k driver is in use. Adrian Chadd remarked that this problem
happens on systems that have ASPM disabled.

To do not hit the bug, skip doing ->config_pci_powersave magic if PCIe
downstream port device, which ath9k device is connected to, has ASPM
disabled.

Bug was introduced by:

commit 53bc7aa0
Author: Vivek Natarajan <vnatarajan@atheros.com>
Date:   Mon Apr 5 14:48:04 2010 +0530

    ath9k: Add support for newer AR9285 chipsets.

Patch should address:
https://bugzilla.kernel.org/show_bug.cgi?id=37462
https://bugzilla.kernel.org/show_bug.cgi?id=37082
https://bugzilla.redhat.com/show_bug.cgi?id=697157

however I did not receive confirmation about that, except from Camilo
Mesias, whose system stops hang regularly with this patch (but still
hangs from time to time, but this is probably some other bug).
Tested-by: NCamilo Mesias <camilo@mesias.co.uk>
Cc: stable@kernel.org # 2.6.35+
Signed-off-by: NStanislaw Gruszka <sgruszka@redhat.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Some devices (e.g. Ubiquiti AirRouter) ship with broken EEPROM chainmask
data, which breaks the initial calibration after a hardware reset.
To fix this, mask the eeprom chainmask with the chainmask of the chip,
and use the chip chainmask if the result is zero.
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Now that the clock rate is initialized properly and SIFS, EIFS, USEC,
slot time and ACK timeout are properly calculated by the generic code,
the 'async FIFO' register hacks are no longer necessary.
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Initialize the the clock-to-TSF field of AR_USEC and the SIFS and EIFS time
registers based on the clock rate instead of relying on initvals.
With those changes, some of the hardcoded AR9287 1.3+ specific overrides
can be dropped.
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>