1. 13 3月, 2012 3 次提交
  2. 11 2月, 2012 4 次提交
  3. 03 2月, 2012 1 次提交
  4. 06 1月, 2012 1 次提交
  5. 18 10月, 2011 1 次提交
  6. 17 10月, 2011 1 次提交
  7. 13 10月, 2011 1 次提交
  8. 29 9月, 2011 1 次提交
  9. 24 9月, 2011 2 次提交
  10. 17 9月, 2011 2 次提交
  11. 16 9月, 2011 2 次提交
  12. 29 8月, 2011 1 次提交
  13. 27 8月, 2011 1 次提交
  14. 19 8月, 2011 2 次提交
  15. 11 8月, 2011 1 次提交
  16. 22 7月, 2011 4 次提交
  17. 25 6月, 2011 3 次提交
  18. 24 6月, 2011 2 次提交
  19. 21 6月, 2011 1 次提交
    • J
      ixgbe: DCB use existing TX and RX queues · e901acd6
      John Fastabend 提交于
      The number of TX and RX queues allocated depends on the device
      type, the current features set, online CPUs, and various
      compile flags.
      
      To enable DCB with multiple queues and allow it to coexist with
      all the features currently implemented it has to setup a valid
      queue count. This is done at init time using the FDIR and RSS
      max queue counts and allowing each TC to allocate a queue per
      CPU.
      
      DCB will now use available queues up to (8 x TCs) this is somewhat
      arbitrary cap but allows DCB to use up to 64 queues. Its easy to
      increase this later if that is needed.
      
      This is prep work to enable Flow Director with DCB. After this
      DCB can easily coexist with existing features and no longer
      needs its own DCB feature ring.
      Signed-off-by: NJohn Fastabend <john.r.fastabend@intel.com>
      Tested-by: NRoss Brattain <ross.b.brattain@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      e901acd6
  20. 15 5月, 2011 6 次提交