1. 12 9月, 2006 1 次提交
  2. 08 9月, 2006 1 次提交
  3. 30 8月, 2006 1 次提交
    • D
      [SPARC64]: Fix X server hangs due to large pages. · 47f2c360
      David S. Miller 提交于
      This problem was introduced by changeset
      14778d90
      
      Unlike the hugetlb code paths, the normal fault code is not setup to
      propagate PTE changes for large page sizes correctly like the ones we
      make for I/O mappings in io_remap_pfn_range().
      
      It is absolutely necessary to update all sub-ptes of a largepage
      mapping on a fault.  Adding special handling for this would add
      considerably complexity to tlb_batch_add().  So let's just side-step
      the issue and forcefully dirty any writable PTEs created by
      io_remap_pfn_range().
      
      The only other real option would be to disable to large PTE code of
      io_remap_pfn_range() and we really don't want to do that.
      
      Much thanks to Mikael Pettersson for tracking down this problem and
      testing debug patches.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      47f2c360
  4. 25 7月, 2006 1 次提交
  5. 22 7月, 2006 5 次提交
  6. 15 7月, 2006 3 次提交
  7. 13 7月, 2006 5 次提交
    • D
      [SPARC]: Fix OF register translations under sub-PCI busses. · a83f9823
      David S. Miller 提交于
      There is an implicit assumption in the code that ranges will translate
      to something that can fit in 2 32-bit cells, or a 64-bit value.  For
      certain kinds of things below PCI this isn't necessarily true.
      
      Here is what the relevant OF device hierarchy looks like for one of
      the serial controllers on an Ultra5:
      
          Node 0xf005f1e0
              ranges:      00000000.00000000.00000000.000001fe.01000000.00000000.01000000
                           01000000.00000000.00000000.000001fe.02000000.00000000.01000000
                           02000000.00000000.00000000.000001ff.00000000.00000001.00000000
                           03000000.00000000.00000000.000001ff.00000000.00000001.00000000
              device_type:  'pci'
              model:  'SUNW,sabre'
      
              Node 0xf005f9d4
                  device_type:  'pci'
                  model:  'SUNW,simba'
      
                 Node 0xf0060d24
                      ranges:  00000010.00000000 82010810.00000000.f0000000 01000000
      			 00000014.00000000 82010814.00000000.f1000000 00800000
                      name:  'ebus'
      
                      Node 0xf0062dac
                          reg:  00000014.003083f8.00000008 --> 0x1ff.f13083f8
                          device_type:  'serial'
                          name:  'su'
      
      So the correct translation here is:
      
      1) Match "su" register to second ranges entry of 'ebus', which translates
         into a PCI triplet "82010814.00000000.f1000000" of size 00800000, which
         gives us "82010814.00000000.f13083f8".
      
      2) Pass-through "SUNW,simba" since it lacks ranges property
      
      3) Match "82010814.00000000.f13083f8" to third ranges property of PCI
         controller node 'SUNW,sabre', and we arrive at the final physical
         MMIO address of "0x1fff13083f8".
      
      Due to the 2-cell assumption, we couldn't translate to a PCI 3-cell
      value, and we couldn't perform a pass-thru on it either.
      
      It was easiest to just stop splitting the ranges application operation
      between two methods, ->map and ->translate, and just let ->map do all
      the work.  That way it would work purely on 32-bit cell arrays instead
      of having to "return" some value like a u64.
      
      It's still not %100 correct because the out-of-range check is still
      done using the 64 least significant bits of the range and address.
      But it does work for all the cases I've thrown at it so far.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a83f9823
    • D
      [SPARC64]: Refine Sabre wsync logic. · 9bbd952e
      David S. Miller 提交于
      It is only needed when there is a PCI-PCI bridge sitting
      between the device and the PCI host controller which is
      not a Simba APB bridge.
      
      Add logic to handle two special cases:
      
      1) device behind EBUS, which sits on PCI
      2) PCI controller interrupts
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9bbd952e
    • D
      [SPARC64]: Fix 2 bugs in sabre_irq_build() · a23c3a86
      David S. Miller 提交于
      When installing the IRQ pre-handler, we were not setting up the second
      argument correctly.  It should be a pointer to the sabre_irq_data, not
      the config space PIO address.
      
      Furthermore, we only need this pre-handler installed if the device
      sits behind a PCI bridge that is not Sabre or Simba/APB.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a23c3a86
    • D
      [SPARC64]: Update defconfig. · 17556fe8
      David S. Miller 提交于
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      17556fe8
    • A
      [SPARC64]: of_device_register() error checking fix · 6cc8b6f5
      Andrew Morton 提交于
      device_create_file() can fail.  This causes the sparc64 compile to
      fail when my fanatical __must_check patch is applied, due to -Werror.
      
      [ Added necessary identical fix for sparc32. -DaveM]
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6cc8b6f5
  8. 11 7月, 2006 2 次提交
  9. 06 7月, 2006 2 次提交
  10. 03 7月, 2006 1 次提交
  11. 01 7月, 2006 4 次提交
  12. 30 6月, 2006 14 次提交