1. 21 11月, 2014 1 次提交
  2. 14 11月, 2014 1 次提交
  3. 08 11月, 2014 2 次提交
  4. 05 11月, 2014 2 次提交
  5. 03 10月, 2014 2 次提交
  6. 01 10月, 2014 1 次提交
  7. 23 9月, 2014 1 次提交
  8. 19 9月, 2014 1 次提交
  9. 18 9月, 2014 1 次提交
  10. 15 9月, 2014 1 次提交
  11. 03 9月, 2014 1 次提交
  12. 08 8月, 2014 3 次提交
  13. 23 7月, 2014 3 次提交
  14. 19 6月, 2014 1 次提交
  15. 11 6月, 2014 2 次提交
  16. 04 6月, 2014 1 次提交
  17. 20 5月, 2014 9 次提交
  18. 16 5月, 2014 5 次提交
  19. 13 5月, 2014 2 次提交
    • C
      drm/i915/chv: Pipe select change for DP and HDMI · 44f37d1f
      Chon Ming Lee 提交于
      With additional of pipe C, current 1 bit registers for pipe select
      for HDMI and DP are no longer able to gather for 3 pipes. As a result,
      new bits location in the same registers are added.
      
      For HDMI, VLV uses bit 30, CHV uses bit 24-25.
      
      For DP, VLV uses bit 30, CHV uses bit 16-17.
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NChon Ming Lee <chon.ming.lee@intel.com>
      Reviewed-by: NImre Deak <imre.deak@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      44f37d1f
    • C
      drm/i915/chv: Add phy supports for Cherryview · e4a1d846
      Chon Ming Lee 提交于
      Added programming phy layer for CHV based on "Application note for 1273
      CHV Display phy".
      
      v2: Rebase the code and do some cleanup.
      v3: Rework based on Ville review.
          -Fix the macro where the ch info need to swap, and add parens to ?
      	 operator.
      	-Fix wrong bit define for DPIO_PCS_SWING_CALC_0 and
      	 DPIO_PCS_SWING_CALC_1 and rename for meaningful.
          -Add some comments for CHV specific DPIO registers.
          -Change the dp margin registery value to decimal to align with the
      	 doc.
      	-Fix the not clearing some value in vlv_dpio_read before write again.
          -Create new hdmi/dp encoder function for chv instead of share with
      	valleyview.
      v4: Rebase the code after rename the DPIO registers define and upstream
      	change.
          Based on Ville review.
          -For unique transition scale selection, after Ville point out, look
      	 like the doc might wrong for the bit 26.  Use bit 27 for ch0 and
      	 ch1.
      	-Break up some dpio write value into two/three steps for readability.
      	-Remove unrelated change.
          -Add some shift define for some registers instead just give the hex
      	value.
          -Fix a bug where write to wrong VLV_TX_DW3.
      v5: Based on Ville review.
      	- Move tx lane latency optimal setting from chv_dp_pre_pll_enable to
      	  chv_pre_enable_dp, and chv_hdmi_pre_pll_enable to
      	  chv_hdmi_pre_enable respectively.
       	- Fix typo in one margin_reg_value for DP_TRAIN_VOLTAGE_SWING_400.
      	- Clear DPIO_TX_UNIQ_TRANS_SCALE_EN for DP and HDMI.
      	- Mask the old deemph and swing bits for hdmi.
      v6: Remove stub for pre_pll_enable for dp and hdmi.
      Signed-off-by: NChon Ming Lee <chon.ming.lee@intel.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      [vsyrjala: Don't touch panel power sequencing on DP]
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NImre Deak <imre.deak@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      e4a1d846