1. 26 4月, 2007 9 次提交
  2. 17 3月, 2007 1 次提交
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      [SPARC64]: Get DEBUG_PAGEALLOC working again. · d1acb421
      David S. Miller 提交于
      We have to make sure to use base-pagesize TLB entries even during the
      early transition period where we need TLB miss handling but don't have
      the kernel page tables setup yet for the linear region.
      
      Also, it is necessary therefore to not use the 4MB TSB for these
      translations, and instead use the normal kernel TSB.  This allows us
      to also get rid of the 4MB tsb for debug builds which shrinks the
      kernel a little bit.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d1acb421
  3. 13 2月, 2007 1 次提交
  4. 12 2月, 2007 1 次提交
  5. 01 1月, 2007 1 次提交
  6. 08 12月, 2006 1 次提交
  7. 27 9月, 2006 1 次提交
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      [SPARC64]: Kill bogus check from bootmem_init(). · 715a0ecc
      David S. Miller 提交于
      There is an ancient and totally incorrect sanity check being
      done on the ramdisk location.  The check assumes that the
      kernel is always loaded to physical address zero, which is
      wrong.  It was trying to validate the ramdisk value by saying that
      if it fell within the kernel image address range it must be wrong.
      
      Anyways, kill this because it actually creates problems.  The
      'ramdisk_image' should always be adjusted down by KERNBASE.
      SILO can easily put the ramdisk in a location which causes
      this test to trigger, breaking things.
      
      [ Based almost entirely upon a patch from Ben Collins. ]
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      715a0ecc
  8. 01 7月, 2006 1 次提交
  9. 28 6月, 2006 1 次提交
  10. 26 6月, 2006 1 次提交
  11. 24 6月, 2006 3 次提交
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      [SPARC64]: Fix for Niagara memory corruption. · c2a5a46b
      David S. Miller 提交于
      On some sun4v systems, after netboot the ethernet controller and it's
      DMA mappings can be left active.  The net result is that the kernel
      can end up using memory the ethernet controller will continue to DMA
      into, resulting in corruption.
      
      To deal with this, we are more careful about importing IOMMU
      translations which OBP has left in the IO-TLB.  If the mapping maps
      into an area the firmware claimed was free and available memory for
      the kernel to use, we demap instead of import that IOMMU entry.
      
      This is going to cause the network chip to take a PCI master abort on
      the next DMA it attempts, if it has been left going like this.  All
      tests show that this is handled properly by the PCI layer and the e1000
      drivers.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c2a5a46b
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      [SPARC64]: Minor bug fix to obp_read_memory(). · 486ad10a
      David S. Miller 提交于
      If we end up zero'ing out the size of one of the entries,
      pop it out of the array completely because some code that
      examines these things cannot handle a zero length element
      properly.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      486ad10a
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      [SPARC64]: Import OBP device tree into kernel data structures. · 372b07bb
      David S. Miller 提交于
      The basic framework is based on the PowerPC OF code.
      
      This code even tries to get the device addressing components
      correct in the full path names.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      372b07bb
  12. 23 3月, 2006 1 次提交
  13. 22 3月, 2006 2 次提交
  14. 20 3月, 2006 16 次提交
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      [SPARC64]: Allow CONFIG_MEMORY_HOTPLUG to build. · 88d70794
      David S. Miller 提交于
      online_page() is straightforward, and then add a dummy
      remove_memory() that returns -EINVAL just like i386.
      
      There is no point in implementing remove_memory() since
      __remove_pages() has no implementation either.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      88d70794
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      [SPARC64]: Use SLAB caches for TSB tables. · 9b4006dc
      David S. Miller 提交于
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9b4006dc
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      [SPARC64]: Fix and re-enable dynamic TSB sizing. · 7a1ac526
      David S. Miller 提交于
      This is good for up to %50 performance improvement of some test cases.
      The problem has been the race conditions, and hopefully I've plugged
      them all up here.
      
      1) There was a serious race in switch_mm() wrt. lazy TLB
         switching to and from kernel threads.
      
         We could erroneously skip a tsb_context_switch() and thus
         use a stale TSB across a TSB grow event.
      
         There is a big comment now in that function describing
         exactly how it can happen.
      
      2) All code paths that do something with the TSB need to be
         guarded with the mm->context.lock spinlock.  This makes
         page table flushing paths properly synchronize with both
         TSB growing and TLB context changes.
      
      3) TSB growing events are moved to the end of successful fault
         processing.  Previously it was in update_mmu_cache() but
         that is deadlock prone.  At the end of do_sparc64_fault()
         we hold no spinlocks that could deadlock the TSB grow
         sequence.  We also have dropped the address space semaphore.
      
      While we're here, add prefetching to the copy_tsb() routine
      and put it in assembler into the tsb.S file.  This piece of
      code is quite time critical.
      
      There are some small negative side effects to this code which
      can be improved upon.  In particular we grab the mm->context.lock
      even for the tsb insert done by update_mmu_cache() now and that's
      a bit excessive.  We can get rid of that locking, and the same
      lock taking in flush_tsb_user(), by disabling PSTATE_IE around
      the whole operation including the capturing of the tsb pointer
      and tsb_nentries value.  That would work because anyone growing
      the TSB won't free up the old TSB until all cpus respond to the
      TSB change cross call.
      
      I'm not quite so confident in that optimization to put it in
      right now, but eventually we might be able to and the description
      is here for reference.
      
      This code seems very solid now.  It passes several parallel GCC
      bootstrap builds, and our favorite "nut cruncher" stress test which is
      a full "make -j8192" build of a "make allmodconfig" kernel.  That puts
      about 256 processes on each cpu's run queue, makes lots of process cpu
      migrations occur, causes lots of page table and TLB flushing activity,
      incurs many context version number changes, and it swaps the machine
      real far out to disk even though there is 16GB of ram on this test
      system. :-)
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      7a1ac526
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      [SPARC64]: Fix 32-bit truncation which broke sparsemem. · 17b0e199
      David S. Miller 提交于
      The page->flags manipulations done by the D-cache dirty
      state tracking was broken because the constants were not
      marked with "UL" to make them 64-bit, which means we were
      clobbering the upper 32-bits of page->flags all the time.
      
      This doesn't jive well with sparsemem which stores the
      section and indexing information in the top 32-bits of
      page->flags.
      
      This is yet another sparc64 bug which has been with us
      forever.
      
      While we're here, tidy up some things in bootmem_init()
      and paginig_init():
      
      1) Pass min_low_pfn to init_bootmem_node(), it's identical
         to (phys_base >> PAGE_SHIFT) but we should use consistent
         with the variable names we print in CONFIG_BOOTMEM_DEBUG
      
      2) max_mapnr, although no longer used, was being set
         inaccurately, we shouldn't subtract pfn_base any more.
      
      3) All the games with phys_base in the zones_*[] arrays
         we pass to free_area_init_node() are no longer necessary.
      
      Thanks to Josh Grebe and Fabbione for the bug reports
      and testing.  Fix also verified locally on an SB2500
      which had a memory layout that triggered the same problem.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      17b0e199
    • D
      [SPARC64]: Move over to sparsemem. · d1112018
      David S. Miller 提交于
      This has been pending for a long time, and the fact
      that we waste a ton of ram on some configurations
      kind of pushed things over the edge.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d1112018
    • D
      [SPARC64]: Bulletproof MMU context locking. · a77754b4
      David S. Miller 提交于
      1) Always spin_lock_init() in init_context().  The caller essentially
         clears it out, or copies the mm info from the parent.  In both
         cases we need to explicitly initialize the spinlock.
      
      2) Always do explicit IRQ disabling while taking mm->context.lock
         and ctx_alloc_lock.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a77754b4
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      [SPARC64]: Fix loop termination in mark_kpte_bitmap() · f7c00338
      David S. Miller 提交于
      If we were aligned, but didn't have at least 256MB left
      to process, we would loop forever.
      
      Thanks to fabbione for the report and testing the fix.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      f7c00338
    • D
      [SPARC64]: Simplify TSB insert checks. · 74ae9987
      David S. Miller 提交于
      Don't try to avoid putting non-base page sized entries
      into the user TSB.  It actually costs us more to check
      this than it helps.
      
      Eventually we'll have a multiple TSB scheme for user
      processes.  Once a process starts using larger pages,
      we'll allocate and use such a TSB.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      74ae9987
    • D
      [SPARC64]: Avoid dcache-dirty page state management on sun4v. · 7a591cfe
      David S. Miller 提交于
      It is totally wasted work, since we have no D-cache aliasing
      issues on sun4v.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      7a591cfe
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      [SPARC64]: Fix TLB context allocation with SMT style shared TLBs. · a0663a79
      David S. Miller 提交于
      The context allocation scheme we use depends upon there being a 1<-->1
      mapping from cpu to physical TLB for correctness.  Chips like Niagara
      break this assumption.
      
      So what we do is notify all cpus with a cross call when the context
      version number changes, and if necessary this makes them allocate
      a valid context for the address space they are running at the time.
      
      Stress tested with make -j1024, make -j2048, and make -j4096 kernel
      builds on a 32-strand, 8 core, T2000 with 16GB of ram.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a0663a79
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      [SPARC64]: Export _PAGE_E and _PAGE_CACHE to modules. · b2bef442
      David S. Miller 提交于
      SBUS flash driver needs it.
      
      Noticed by Fabbione.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b2bef442
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      [SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings. · d7744a09
      David S. Miller 提交于
      It can map all of the linear kernel mappings with zero TSB hash
      conflicts for systems with 16GB or less ram.  In such cases, on
      SUN4V, once we load up this TSB the first time with all the
      mappings, we never take a linear kernel mapping TLB miss ever
      again, the hypervisor handles them all.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d7744a09
    • D
      [SPARC64]: Make use of Niagara 256MB PTEs for kernel mappings. · 9cc3a1ac
      David S. Miller 提交于
      We use a bitmap, one bit for every 256MB of memory.  If the
      bit is set we can use a 256MB PTE for linear mappings, else
      we have to use a 4MB PTE.
      
      SUN4V support is there, and we can very easily add support
      for Panther cpu 256MB PTEs in the future.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9cc3a1ac
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      [SPARC64]: Export a PAGE_SHARED symbol. · 0f15952a
      David S. Miller 提交于
      For drivers/media/*, noticed by Fabbione.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0f15952a
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      [SPARC64]: More TLB/TSB handling fixes. · 8b234274
      David S. Miller 提交于
      The SUN4V convention with non-shared TSBs is that the context
      bit of the TAG is clear.  So we have to choose an "invalid"
      bit and initialize new TSBs appropriately.  Otherwise a zero
      TAG looks "valid".
      
      Make sure, for the window fixup cases, that we use the right
      global registers and that we don't potentially trample on
      the live global registers in etrap/rtrap handling (%g2 and
      %g6) and that we put the missing virtual address properly
      in %g5.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8b234274
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      12e126ad