I just added an I2C dependency to the wm8985 driver to work around
a build failure, but it turns out that was premature: we actually
need to depend on SND_SOC_I2C_AND_SPI, as the driver can work with either
of the two, and we only need to prevent a configuration that has
I2C=m and SND_SOC_WM8985=y.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: 05252513 ("ASoC: wm8985: add i2c dependency")
Signed-off-by: NMark Brown <broonie@kernel.org>

The wm8985 driver is now user-selectable, but building it with
I2C disabled results in a link failure:

sound/built-in.o: In function `wm8985_i2c_probe':
:(.text+0x44914): undefined reference to `__devm_regmap_init_i2c'
sound/built-in.o: In function `wm8985_exit':
:(.exit.text+0x3d8): undefined reference to `i2c_del_driver'
sound/built-in.o: In function `wm8985_modinit':
:(.init.text+0x1454): undefined reference to `i2c_register_driver'

This adds a Kconfig dependency the way that the other codec
drivers have it.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: 811e66de ("ASoC: wm8985: add support for WM8758")
Signed-off-by: NMark Brown <broonie@kernel.org>

The WM8758 chip is almost identical to WM8985 with the difference that it
doesn't feature the AUX input. This patch adds the WM8758 support into the
WM8985 driver.

The chip selection is done by the I2C name. The SPI probe supports only
the WM8985.
Signed-off-by: NPetr Kulhavy <petr@barix.com>
Reviewed-by: NCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The WM8758 chip is almost identical to WM8985 with the difference that it
doesn't feature the AUX input. This patch adds the register definitions
for WM8758 specific bit fields to the header file.
Signed-off-by: NPetr Kulhavy <petr@barix.com>
Acked-by: NCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Happened when the Playback (or Capture) is running continuously
and Capture (or Playback) is restarted (xrun, manual stop/start...)

Since the RX (or TX) FIFO are only reset when the whole SSI is disabled,
pending samples from previous capture (or playback) session may still
be present. They must be erased to not introduce channel slipping.

FIFO Clear register fields are documented in IMX51, IMX35 reference manual.
They are not documented in IMX50 or IMX6 RM, despite they are
working as expected on IMX6SL and IMX6solo.
Signed-off-by: NArnaud Mouiche <arnaud.mouiche@invoxia.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Tested-by: NCaleb Crome <caleb@crome.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Previously, SCR.SSIEN and SCR.TE were enabled at once if no capture
stream was also running.
This may not give a chance for the DMA to write the first sample in
TX FIFO before the streaming starts on the PCM bus, inserting void
samples first.
Those void samples are then responsible for slipping the channels.
Signed-off-by: NArnaud Mouiche <arnaud.mouiche@invoxia.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Tested-by: NCaleb Crome <caleb@crome.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

If the capture is already running while playback is started, it is highly
probable (>80% in a 8 channels scenario) that samples are lost between
the DMA and TX fifo.

The reason is that SIER.TDMAE is set before STCR.TFEN0, leaving a time
window where the FIFO doesn't receive the samples written by the DMA.

This particular case happened only if capture is already enabled as
SCR.SSIEN is already set at the playback startup instant.
Signed-off-by: NArnaud Mouiche <arnaud.mouiche@invoxia.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Tested-by: NCaleb Crome <caleb@crome.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Most of functions only receive the ssi_private reference and don't have
a knowledge of 'dev' pointer, even for debug purpose.
Signed-off-by: NArnaud Mouiche <arnaud.mouiche@invoxia.com>
Tested-by: NCaleb Crome <caleb@crome.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

im6sl reference manual 47.7.4:
"
Bit clock - Used to serially clock the data bits in and out of the SSI port.
This clock is either generated internally (from SSI's sys clock) or taken
from external clock source (through the Tx/Rx clock ports).
[...]
Care should be taken to ensure that the bit clock frequency (either
internally generated by dividing the SSI's sys clock or sourced from
external device through Tx/Rx clock ports) is never greater than 1/5
of the ipg_clk (from CCM) frequency.
"

Since, in master mode, the sysclk is a multiple of bitclk, we can
easily reach a high sysclk value, whereas keeping a reasonable bitclk.

ex: 8ch x 16bit x 48kHz = 6144000, requires a 24576000 sysclk (PM=1)
    yet ipg_clk/5 = 66Mhz/5 = 13.2
Signed-off-by: NArnaud Mouiche <arnaud.mouiche@invoxia.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Tested-by: NCaleb Crome <caleb@crome.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

The max number of slots in TDM mode is 32:
- Frame Rate Divider Control is a 5bit value
- Time slot mask registers control 32 slots.
Signed-off-by: NArnaud Mouiche <arnaud.mouiche@invoxia.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Tested-by: NCaleb Crome <caleb@crome.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some definitions to support the PCM5102A codec
by Texas Instruments.
Signed-off-by: NFlorian Meier <florian.meier@koalo.de>

Changes to original patch by Florian Meier:
* rebased (Makefile and Kconfig
* fixed checkpath errors (spaces, newlines)
* added dt-binding documentation
Signed-off-by: NMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Manage the hda idisp link using shiny new link APIs.  We need to
keep link On while we probe and also hold the reference in runtime
resume and drop in suspend
Signed-off-by: NJeeja KP <jeeja.kp@intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Use shiny new link APIs to manage the links. Also remove old link
configuration logic from driver.

We need to keep link and cmd dma to off during active suspend
to allow system to enter low power state and turn it on if
the link and cmd dma was on before active suspend in active
resume.
Signed-off-by: NJeeja KP <jeeja.kp@intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The HDA links can be switched off when not is use, similarly
command DMA can be stopped as well. This calls for a reference
counting mechanism on the link by it's users to manage the link
power. The DMA can be turned off when all links are off

For this we add two APIs
	snd_hdac_ext_bus_link_get
	snd_hdac_ext_bus_link_put

They help users to turn up/down link and manage the DMA as well
Signed-off-by: NJeeja KP <jeeja.kp@intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Acked-by: NTakashi Iwai <tiwai@suse.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

Broxton-P reference platform also uses combo jack for audio
connector so we need to set codec pdata to use this based on DMI
match for this board.
Signed-off-by: NRamesh Babu <ramesh.babu@intel.com>
Signed-off-by: NSenthilnathan Veppur <senthilnathanx.veppur@intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Acked-by: NBard Liao <bardliao@realtek.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

ACPI driver data can be NULL so we need to check that before
dereference the driver data.
Signed-off-by: NSenthilnathan Veppur <senthilnathanx.veppur@intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Acked-by: NBard Liao <bardliao@realtek.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Acked-by: NVinod Koul <vinod.koul@intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Format number after 0x in hex.

Cc: Jie Yang <yang.jie@linux.intel.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.com>
Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Current checking for PLL 32KHz mode fails in driver code when
bypassing the PLL. This is due to an incorrect check of PLL
source type when 32KHz clock is provided. Removal of this check
resolves the issue.
Signed-off-by: NAdam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

This update changes the dividers used for ranges of input MCLK
frequencies, to improve PLL locking for a corner case when at edge
of MCLK frequency input divider range.
Signed-off-by: NAdam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Currently PC counter is always synchronised to DAI which means that
when the DAI is disabled, features such as ALC calibration cannot
be executed successfully. This patch makes sure that when the DAI
is disabled, PC counter is set to free-running.
Signed-off-by: NAdam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

When the codec is DAI clk slave, and the SRM feature of the PLL
is being used, the enabling of the DAI should occur only after
the PLL has locked to the incoming WCLK. This update adds checking
to the the DAI widget event, so it waits for SRM to lock. There is
also a timeout if that lock doesn't occur within a given time.
Signed-off-by: NAdam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Currently, when Codec is I2S master DAI clocks are continuously
generated even if all audio streams have stopped. To improve
efficiency, control of the DAI clocks for master mode have been
moved to a DAPM widget event so they're only enabled as required.
Signed-off-by: NAdam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

This patch adds the Broxton-P machine driver for Intel Broxton-P
reference boards. This machine uses the RT298 codec
Signed-off-by: NRamesh Babu <ramesh.babu@intel.com>
Signed-off-by: NSenthilnathan Veppur <senthilnathanx.veppur@intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The Broxton-P platform has 6 SSPs so we need to add ssp2 thru
ssp5 to DAI list for the driver.
Signed-off-by: NPardha Saradhi K <pardha.saradhi.kesapragada@intel.com>
Signed-off-by: NRamesh Babu <ramesh.babu@intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Although the ES8328 does support different rates for capture and
playback, only very limited combinations are supported (8kHz and 48kHz
or 8.0182kHz and 44.1kHz) with most rates required to be symmetric.

Instead of adding a lot of complexity for little gain, let's enforce
symmetric rates.
Signed-off-by: NJohn Keeping <john@metanate.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Signed-off-by: NJohn Keeping <john@metanate.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The values are the same for the DAC and ADC so remove the specific
values and use values with shifts.
Signed-off-by: NJohn Keeping <john@metanate.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

This is a refactor in preparation for supporting more sample sizes which
has no functional change.
Signed-off-by: NJohn Keeping <john@metanate.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The chip only supports single reads and writes.
Signed-off-by: NJohn Keeping <john@metanate.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

This is always used along with ES8328_CONTROL1_ENREF so there is no
change in the generated code as a result of this fix.
Signed-off-by: NJohn Keeping <john@metanate.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The ADCCONTROL4 and DACCONTROL1 registers are similar but not identical,
with the DACCONTROL1 having each field starting one bit higher than
ADCCONTROL4.

Instead of introducing a magic shift, add new constants for the values
in ADCCONTROL4 and use a second variable to setup the ADC.
Signed-off-by: NJohn Keeping <john@metanate.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

This ensures that the clock is setup after its frequency has been set;
the existing code in set_dai_fmt may be called before the clock rate has
been set resulting in an incorrect configuration.
Signed-off-by: NJohn Keeping <john@metanate.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

If the McASP is used as clock master and the reference clock is AUXCLK we
can have additional level of divider. The BCLK divider is limited to
maximum 32, if the desired bclk can not be reached with this, the AUXCLK
divider also needs to be used.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Change the return value to error_pmm instead of the BCLK div and handle the
divider configuration to McASP within the function when the set flag is
true.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Change the first parameter to struct davinci_mcasp* from
struct snd_soc_dai*
The function internally does not use or need the DAI information.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Instead of hardwired IDs add defines for the available dividers.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Make sure that the user can not start multiple streams with the same
direction.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Reported-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NMark Brown <broonie@kernel.org>

During skl_nhlt_init(), acpi obj pointer is allocated and never
freed and remap address is not unmapped.

To fix this we should release the ACPI obj and also unmap the
nhlt address during cleanup of driver.
Signed-off-by: NJeeja KP <jeeja.kp@intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>