The L2C-220 (AKA L220) and L2C-310 (AKA PL310) cache controllers feature
a Performance Monitoring Unit (PMU), which can be useful for tuning
and/or debugging. This hardware is always present and the relevant
registers are accessible to non-secure accesses. Thus, no special
firmware interface is necessary.

This patch adds support for the PMU, plugging into the usual perf
infrastructure. The overflow interrupt is not always available (e.g. on
RealView PBX A9 it is not wired up at all), and the hardware counters
saturate, so the driver does not make use of this. Instead, the driver
periodically polls and reset counters as required to avoid losing
events due to saturation.
Signed-off-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NPawel Moll <pawel.moll@arm.com>
Tested-by: NKim Phillips <kim.phillips@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

According to ARM AN321 (section 4.12):

"If the vector table is in writable memory such as SRAM, either relocated
by VTOR or a device dependent memory remapping mechanism, then
architecturally a memory barrier instruction is required after the vector
table entry is updated, and if the exception is to be activated
immediately"
Reviewed-by: NVladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Cortex-M7 is a new member of the V7M processor family that adds, among
other things, caches over the features available in Cortex-M4.

This patch adds support for recognising the processor at boot time, and
make use of recently introduced cache functions.
Signed-off-by: NJonathan Austin <jonathan.austin@arm.com>
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: NAndras Szemzo <sza@esh.hu>
Tested-by: NJoachim Eastwood <manabian@gmail.com>
Tested-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch copies the method used for V7A/R CPUs to specify differing
processor info for different cores.

This patch differentiates Cortex-M3 and Cortex-M4 and leaves a fallback case
for any other V7M processors.
Signed-off-by: NJonathan Austin <jonathan.austin@arm.com>
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: NAndras Szemzo <sza@esh.hu>
Tested-by: NJoachim Eastwood <manabian@gmail.com>
Tested-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch does the plumbing required to invoke the V7M cache code added
in earlier patches in this series, although there is no users for that
yet.

In order to honour the I/D cache disable config options, this patch changes
the mechanism by which the CCR is set on boot, to be more like V7A/R.
Signed-off-by: NJonathan Austin <jonathan.austin@arm.com>
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: NAndras Szemzo <sza@esh.hu>
Tested-by: NJoachim Eastwood <manabian@gmail.com>
Tested-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This commit implements the cache operation for V7M.

It is based on V7 counterpart and differs as follows:
- cache operations are memory mapped
- only Thumb instruction set is supported
- we don't handle user access faults
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: NAndras Szemzo <sza@esh.hu>
Tested-by: NJoachim Eastwood <manabian@gmail.com>
Tested-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Commit 8e43a905 "ARM: 7325/1: fix v7 boot with lockdep enabled"
introduced notrace variant of save_and_disable_irqs to balance notrace
variant of restore_irqs; however V7M case has been missed. It was not
noticed because cache-v7.S the only place where notrace variant is used.
So fix it, since we are going to extend V7 cache routines to handle V7M
case too.
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: NAndras Szemzo <sza@esh.hu>
Tested-by: NJoachim Eastwood <manabian@gmail.com>
Tested-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

With the addition of caches to the V7M Architecture a new Cache Type
Register (CTR) is defined at 0xE000ED7C. This register serves the same
purpose as the V7A/R version and accessed via the read_cpuid_cachetype.
Signed-off-by: NJonathan Austin <jonathan.austin@arm.com>
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: NAndras Szemzo <sza@esh.hu>
Tested-by: NJoachim Eastwood <manabian@gmail.com>
Tested-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

V7M implements cache operations similarly to V7A/R, however all operations
are performed via memory-mapped IO instead of co-processor operations.

This patch adds register definitions relevant to the V7M ARM architecture's
cache architecture.
Signed-off-by: NJonathan Austin <jonathan.austin@arm.com>
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: NAndras Szemzo <sza@esh.hu>
Tested-by: NJoachim Eastwood <manabian@gmail.com>
Tested-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Currently we use raw cp15 operations to access the cache setup data.

This patch abstracts the CSSELR and CCSIDR accessors out to a header so
that the implementation for them can be switched out as we do with other
cpu/cachetype operations.
Signed-off-by: NJonathan Austin <jonathan.austin@arm.com>
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: NAndras Szemzo <sza@esh.hu>
Tested-by: NJoachim Eastwood <manabian@gmail.com>
Tested-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch removes the unused secure_flush_area function.  The only
consumer of this function has moved to using the streaming DMA APIs.
Signed-off-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Document the UNCACHEABLE_ADDR definitions for footbridge and SA1100
so that we know where they're located and/or what they're accessing.
Change RiscPC to calculate the UNCACHEABLE_ADDR value from FLUSH_BASE
as that's where we locate that.

UNCACHEABLE_ADDR is used to perform an uncached access (ARMv4
terminology) necessary to force a CPU clock-switch to the memory-
speed clock, as required for entering WFI.
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>

Move the StrongARM CPU ID checks out of the platform's hardware.h
file into asm/cputype.h
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>

Even though perf_ops_bp was removed/renamed back in commit
b0a873eb ("perf: Register PMU implementations"), as part of
v2.6.37, its definition still lives on in some arch headers.

This patch removes the vestigal definition from arm.
Signed-off-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NWill Deacon <will.deacon@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

vdso_data_mapping is never modified, so mark it as const.

vdso_total_pages, vdso_data_page, vdso_text_mapping and cntvct_ok are
initialized by vdso_init(), thereafter are read only.

The fact that they are read only after init makes them candidates for
__ro_after_init declarations.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Reviewed-by: NKees Cook <keescook@chromium.org>
Acked-by: NNathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Guided by grsecurity's analogous __read_only markings in arch/arm,
this applies several uses of __ro_after_init to structures that are
only updated during __init.
Signed-off-by: NKees Cook <keescook@chromium.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Now that the generic changes are in place, this can be enabled on ARM
with the use of proper user space accessors in the flat_get_addr_from_rp()
and flat_put_addr_at_rp() handlers as rp actually holds a user space
address.
Signed-off-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

As per L2C-310 TRM[1]:

"... You can control this feature using bits 30,27 and 23 of the
Prefetch Control Register. Bit 23 and 27 are only used if you set bit 30
HIGH..."

which means there is no need to clear bit 23 if bit 30 is being cleared.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246e/CJAJACBJ.htmlAcked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Replace magic numbers used for L310 Prefetch Control Register
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The last ad-hoc __phys_to_virt definition was removed in commit fd0053c9
("ARM: realview: remove sparsemem hack"). Therefore we can remove the
unneeded definitions and unduplicate the virt_to_pfn macro from
asm/memory.h.
Signed-off-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

We currently define OBJCOPYFLAGS in the top-level arm Makefile, and thus
these flags will be passed to all uses of objcopy, kernel-wide, for
which they are not explicitly overridden. The flags we set are intended
for converting a few ELF files into raw binaries, and thus the flags
chosen are problematic for some other uses which do not expect a raw
binary result, e.g. the upcoming lkdtm rodata test:

  http://www.openwall.com/lists/kernel-hardening/2016/06/08/2

This patch localises the objcopy flags such that they are only used for
the cases we require them for today.
Signed-off-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NKees Cook <keescook@chromium.org>
Tested-by: NLaura Abbott <labbott@redhat.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

According to Documentation/printk-formats.txt when printing
a size_t variable we should use %zu or %zx format specifiers.

As we are printing a memory size value, we should better use %zu
in this case.
Reported-by: NFrank Mori Hess <fmh6jj@gmail.com>
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NRich Felker <dalias@libc.org>

This defconfig is intended not to be specific to a particular board;
it enables drivers for all currently-supported hardware, and should be
updated to include additional drivers as they are added.
Signed-off-by: NRich Felker <dalias@libc.org>

Enable common clk framework for DT-based boards and disable code that
depends on the legacy sh clk framework when common clk is enabled.
Once legacy drivers are converted over, the old code can be removed
entirely.
Signed-off-by: NRich Felker <dalias@libc.org>

Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NRich Felker <dalias@libc.org>

The mempool_destroy() function tests whether its argument is NULL
and then returns immediately. Thus the test around the calls is not needed.

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NRich Felker <dalias@libc.org>

Signed-off-by: NRich Felker <dalias@libc.org>

Support is hooked up via a cpu start method specified in the device
tree, and also depends on DT nodes that describe the interfaces for
performing IPI and identifying which cpu execution is taking place on.
The currently used method is a form of spin table, where secondary
cpus are unblocked by writing to a special address.
Signed-off-by: NRich Felker <dalias@libc.org>

The SH2 version of entry.S uses global variables, which need to be
cpu-local in order to work with SMP. For ease of access from asm,
simply use arrays indexed by cpu number, and require the availability
of an address (mmio register or properly setup per-cpu memory) from
which the current cpu's index can be read.
Signed-off-by: NRich Felker <dalias@libc.org>

The version of futex.h in asm-generic should really be adapted to do
the same thing so that this hideous code does not have to be
duplicated per-arch.
Signed-off-by: NRich Felker <dalias@libc.org>

Signed-off-by: NRich Felker <dalias@libc.org>

The J-Core cpu has, as an ISA extension, an atomic compare-and-swap
instruction cas.l which applications need to use (instead the imask or
gusa atomic models, which are fundamentally limited to UP) for
synchronization in order to be compatible with SMP systems. Provide a
hwcap flag so that it's possible to do runtime selection and support
both.
Signed-off-by: NRich Felker <dalias@libc.org>

At the CPU/ISA level, the J2 is compatible with SH-2, and thus the
changes to add J2 support build on existing SH-2 support. However, J2
does not duplicate the memory-mapped SH-2 features like the cache
interface. Instead, the cache interfaces is described in the device
tree, and new code is added to be able to access the flat device tree
at early boot before it is unflattened.

Support is also added for receiving interrupts on trap numbers in the
range 16 to 31, since the J-Core aic1 interrupt controller generates
these traps. This range was unused but nominally for hardware
exceptions on SH-2, and a few values in this range were used for
exceptions on SH-2A, but SH-2A has its own version of the relevant
code.

No individual cpu subtypes are added for J2 since the intent moving
forward is to represent SoCs with device tree rather than as
hard-coded subtypes in the kernel. The CPU_SUBTYPE_J2 Kconfig item
exists only to fit into the existing cpu selection mechanism until it
is overhauled.
Signed-off-by: NRich Felker <dalias@libc.org>

We should set the error code here rather than incorrectly returning 0.
Otherwise static checkers complain.

Link: http://lkml.kernel.org/r/20160804053525.GM775@mwandaSigned-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Alexandre Bounine <alexandre.bounine@idt.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The LNKGET based atomic sequence in __cmpxchg_u32 has slightly incorrect
constraints for the return value which under certain circumstances can
allow an address unit register to be used as the first operand of a CMP
instruction. This isn't a valid instruction however as the encodings
only allow a data unit to be specified. This would result in an
assembler error like the following:

  Error: failed to assemble instruction: "CMP A0.2,D0Ar6"

Fix by changing the constraint from "=&da" (assigned, early clobbered,
data or address unit register) to "=&d" (data unit register only).

The constraint for the second operand, "bd" (an op2 register where op1
is a data unit register and the instruction supports O2R) is already
correct assuming the first operand is a data unit register.

Other cases of CMP in inline asm have had their constraints checked, and
appear to all be fine.

Fixes: 6006c0d8 ("metag: Atomics, locks and bitops")
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: linux-metag@vger.kernel.org
Cc: <stable@vger.kernel.org> # 3.9.x-

The jump table can reference text found in an __exit section.  Thus,
instead of discarding it at build time, include EXIT_TEXT as part of
__init and it will be released when the system boots.

Link: http://lkml.kernel.org/r/60284113bb759121e8ae3e99af1535647e52123f.1467837322.git.jbaron@akamai.comSigned-off-by: NJason Baron <jbaron@akamai.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Chris Metcalf <cmetcalf@mellanox.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Joe Perches <joe@perches.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Previously, all the __exit sections were just dropped by the link phase.
However, if there are static_key (jump label) constructs in __exit
sections that are not modules, the link fails with the message:

   `.exit.text' referenced in section `__jump_table' of xxx.o:
   defined in discarded section `.exit.text' of xxx.o

Support this usage by keeping the .exit.text sections in the final image
if JUMP_LABEL is defined, then discarding them once initialization is
complete.

Link: http://lkml.kernel.org/r/bfd7c107c610c30e992868ebfe2a5d796a097464.1467837322.git.jbaron@akamai.comSigned-off-by: NJason Baron <jbaron@akamai.com>
Signed-off-by: NChris Metcalf <cmetcalf@mellanox.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Joe Perches <joe@perches.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The jump table can reference text found in an __exit section.  Thus,
instead of discarding it at build/link time, include EXIT_TEXT as part
of __init and release it at system boot time.

Without this patch the link fails with:

    `.exit.text' referenced in section `__jump_table' of xxx.o:
    defined in discarded section `.exit.text' of xxx.o

Link: http://lkml.kernel.org/r/d822da427ab07a02a394602eca687104ff682f83.1467837322.git.jbaron@akamai.comSigned-off-by: NJason Baron <jbaron@akamai.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Chris Metcalf <cmetcalf@mellanox.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Joe Perches <joe@perches.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The stringify_in_c() macro may not be included. Make the dependency
explicit.

Link: http://lkml.kernel.org/r/564720c5328edd53c9d56db325be7215440eec3e.1467837322.git.jbaron@akamai.comSigned-off-by: NJason Baron <jbaron@akamai.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Joe Perches <joe@perches.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Chris Metcalf <cmetcalf@mellanox.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Joe Perches <joe@perches.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>